Pentium 4 analysis

Our findings comfirm that the Pentium 4 features a 2 cycle latency high bandwidth L1-cache. Small programs with data that fits into the L1-cache should be able to run incredibly fast, even with many dependency chains or low ILP. Of course, there are very few programs that have such small datasets, which can fit in such a small 8KB L1-cache. Most applications rely on both the L1-cache and L2-cache.

Furthermore, the L1 and L2-cache combination is not as good it looks on paper. Without the use of SSE-2, the amount of bandwidth per clock is not any higher than it was on the PIII, despite the claim that the P4 can transfer twice as much data per clock. The average latency of the L1 and L2-cache together is, in absolute time, much lower than it was on the PIII, but when counted in average cycles, it is not such a vast improvement.

This is one reason why it is not so easy for the Pentium 4 to reach the same clock for clock performance as the Pentium III in benchmarks which run mainly in the caches. Even though the paper specs may claim otherwise, a 25% lower clocked Athlon has no significant bandwidth disadvantage if the data fits in the both the L1 and L2-cache.