Architettura Pentium IV

Average memory latency.
The L1-Datacache that is only 8 kb big, but as you know, the Trace cache, which replaces the L1-Instructions cache, can contain 12000 microps. How does this compare to the I-cache of the P6? Let us assume that the average x86 is about 3.5 bytes big and that one x86 is on average decoded in 2 micro-ops. This would mean that the Trace cache can be compared to an equivalent I-cache of about 3.5x12000/2 bytes or 21 KB. When I asked about the average hitrate of the Trace-cache, Doug responded that it is comparable to a conventional I-cache (in most applications about 95-98%). So it is a bit weird that the I-cache is way much bigger than the D-cache. Feel free to comment of course.

Intel claims that the average latency* of the P4 is about 1.8x better than the PIII, if both systems are outfitted with RDRAM. That is pretty amazing considering that the L1-D cache is pretty small, and consequently the L1 miss rate must be relatively high. Does this mean that the L2-cache has a lower latency than the one of the Coppermine P6 (7 cycles)? Intel did not comment on this matter, and I suppose that a lower L2-cache latency could endanger the clockspeed rampability. So this seems to be a small mystery.