[Thread Ufficiale V4.0] AMD K10 Phenom2/Athlon2: L'era dei 45nm AMD!

[JDM70]

Originariamente inviato da capitan_crasy

Sembra che hanno aggiunto un "Northbridge P-states"
Comunque ecco la tabella completa...

Originariamente inviato da Pihippo

Ciao:
Dunque da quello che ne capisco io il c3 introduce:
Un nuovo P-state per il Northbridge, quindi mo sembra che in idle si abbassa la freq anche di esso, quindi vi saranno P-0 Nb a velocità massima e P-1 a velocità dimezzata. Inoltre quando i core sono in C1E( che sempre un p-state se non sbaglio) entreranno nello stato C5 con conseguente flush di L1-L2 nella L3, i core in C5 andranno in ALTVID( che è un metodo per far scendere ancora di più il Vcore nello stato C5) di quanto non so.
Purtroppo non sono in grado di capire che hanno fatto per IPC e performance varie, fatto sta che il C3 ha abbassato i consumi in idle NB che entra in modalità power saving girando a metà della sua velocità e qundi anche la L3 mentre prima era sempre tutto acceso al massimo, ed anche in full
Edit:
Letto dalla tabella e da:http://www.amd.com/us-en/assets/cont...docs/31116.pdf

Ciao capitan_crasy & Pihippo, quello che state dicendo succede già anche a mè con la mobo in firma e bios 1604, di default si imposta a 1.100v ma ho visto che in OC mi provocava instabilità, allora lo portato 1.200v e quando da vista lo setto bilanciato che il procio mi va a 800mhz il voltaggio del vNB ritorna a 1.100v sia con C1E attivo o disattivato, risale a 1.200v solo quando va alla massima frequenza il procio.... il tutto senza usare K10 e C&Q attivo. Allego immagine di K10 che da li si vedono bene i vari PSTATE e vNB.

[MonsterMash]

Originariamente inviato da JDM70

Ciao capitan_crasy & Pihippo, quello che state dicendo succede già anche a mè con la mobo in firma e bios 1604, di default si imposta a 1.100v ma ho visto che in OC mi provocava instabilità, allora lo portato 1.200v e quando da vista lo setto bilanciato che il procio mi va a 800mhz il voltaggio del vNB ritorna a 1.100v sia con C1E attivo o disattivato, risale a 1.200v solo quando va alla massima frequenza il procio.... il tutto senza usare K10 e C&Q attivo. Allego immagine di K10 che da li si vedono bene i vari PSTATE e vNB.

Attualmente si può cambiare il valore del vNB per ogni pstate (con k10stat), la differenza del c3 (se ho capito bene) è che si può cambiare anche il valore della frequenza del NB. In questo modo con il pstate3 puoi settare un NB a 400mhz e magari a 0,5V, così da risparmiare potenza.

[mtk]

Originariamente inviato da Vash_85

Cacchio, io di solito ci monto degli athlon a basso consumo

e ma un htpc lo tieni acceso per un paio d ore al giorno,fai anche 4 per vedere un paio di film e ascoltare un po' di musica....il discorso consumo non mi sembra un dramma....e poi me lo porto dietro anche per i lan party...infatti anche la 8800gt non e' il massimo del risparmio dal lato video

Originariamente inviato da -Maxx-

Dovete vedere questo insolito accrocchio di mobo a base di 785G -clicca-

sta mobo a me servirebbe....ho ancora due 4200x2 e ram ddr400,appena mi muoiono le mobo mi sa che invece di buttare proci e ram li rivitalizzo con questa se non costera' molto.......duro a morire il 939,asrock e' proprio affezionata a sto socket

[JDM70]

Originariamente inviato da MonsterMash

Attualmente si può cambiare il valore del vNB per ogni pstate (con k10stat), la differenza del c3 (se ho capito bene) è che si può cambiare anche il valore della frequenza del NB. In questo modo con il pstate3 puoi settare un NB a 400mhz e magari a 0,5V, così da risparmiare potenza.

Allora Bò mi cucio la bocca pensavo solo ad'una questione di voltaggio... il tutto lo fa da bios senza usare K10

[MonsterMash]

Originariamente inviato da mtk

e ma un htpc lo tieni acceso per un paio d ore al giorno,fai anche 4 per vedere un paio di film e ascoltare un po' di musica....il discorso consumo non mi sembra un dramma....e poi me lo porto dietro anche per i lan party...infatti anche la 8800gt non e' il massimo del risparmio dal lato video

Il problema non è il consumo, ma il calore (e conseguente rumore) e le dimensioni! Come fai a far stare un processore OC + 8800gt in un case grosso quanto un videoregistratore? E poi il rumore delle ventole non ti disturba mentre guardi un film?
Io ho usato un x2 5000+ black edition molto downvoltato su una mobo msi k9a26m (con 780g e uscita hdmi), e ho rallentato tutte le ventole (compresa quella dell'alimentatore micro-atx, altrimenti il rumore mi dava fastidio...

[ATi7500]

Originariamente inviato da JDM70

Ciao capitan_crasy & Pihippo, quello che state dicendo succede già anche a mè con la mobo in firma e bios 1604, di default si imposta a 1.100v ma ho visto che in OC mi provocava instabilità, allora lo portato 1.200v e quando da vista lo setto bilanciato che il procio mi va a 800mhz il voltaggio del vNB ritorna a 1.100v sia con C1E attivo o disattivato, risale a 1.200v solo quando va alla massima frequenza il procio.... il tutto senza usare K10 e C&Q attivo. Allego immagine di K10 che da li si vedono bene i vari PSTATE e vNB.

di che tipo di instabilita' parli? Corruzioni grafiche sul desktop?

[JDM70]

Originariamente inviato da ATi7500

di che tipo di instabilita' parli? Corruzioni grafiche sul desktop?

no se tenevo il vNB a 1.100v era stabile con il NB a 2.200 ma portandolo a 2.400 il NB ho dovuto alzarlo a 1.200 il Vnb... causava blocchi di sistema si Freezava e BSO

[bjt2]

Originariamente inviato da capitan_crasy

Sembra che hanno aggiunto un "Northbridge P-states"
Comunque ecco la tabella completa...

Si deduce che lo step D non supporta il single plane (quindi non andrà su AM2 ma solo su AM2+ e AM3+) e supporta le DDR3...

[capitan_crasy]

Originariamente inviato da bjt2

Si deduce che lo step D non supporta il single plane (quindi non andrà su AM2 ma solo su AM2+ e AM3+) e supporta le DDR3...

Per dirti la verità la cosa non mi dispiace affatto...
Comunque ecco il link del documento sul BIOS and Kernel Developer’s Guide (BKDG) aggiornato al 9 settembre 2009...
Clicca qui...

[bjt2]

Originariamente inviato da capitan_crasy

Sono usciti i documenti tecnici sullo step C3...
Aspettando l'analisi del buon bjt2 posso dire che lo step C3 risolve "Errata 379", cioè viene corretto il BUG dei 4 moduli di memoria DDR3 @ 1333Mhz...

Quel documento comprende anche lo step D...

Ecco un riassunto degli errata:

Errata corretti nel C3 e nel D:
362,379,395

Errata corretti solo nello step D (PRESENTI ANCORA NELLO STEP C3):
346,352,353,354,359,378,382,407

Errata ancora non corretti nello step C3 e D:
327,343,344,350,361,372,388,391,396,400

Errata nuovi dello step D (NON PRESENTI NEGLI STEP PRECEDENTI):
374,384,385,386,389,397,398



Nel dettaglio:

327 NON Corretto sia nel C3 che nel D
HyperTransport™ Link RTT Specification Violation
Description
The RTT specification for the HyperTransport™ link may be violated on some processor revisions.
Potential Effect on System
These violations do not result in any other HyperTransport™ link electrical specification violations. There are no known functional failures related to this problem.
Suggested Workaround
BIOS should set the Link Phy Impedance Register[RttCtl] (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and Link Phy Impedance Register[RttIndex] (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b.
Fix Planned
Yes

In breve: probelma elettrico sul link HTT che sembra senza conseguenze.

343 NON Corretto sia nel C3 che nel D
Eviction May Occur When Using L2 Cache as General Storage During Boot
Description
When system software is using the L2 cache as general storage before memory initialization, the processor may determine during speculative execution that data destined for the instruction cache is dirty. The processor will then evict these cache lines, resulting in lost data.
Potential Effect on System
System software using L2 cache as general storage before memory initialization may experience unpredictable system behavior.
Suggested Workaround
System software should set MSRC001_102A[35] to 1b prior to using L2 cache as general storage during boot. System software should clear MSRC001_102A[35] to 0b after the L2 cache is no longer used as general storage.
Fix Planned
No

In breve: durante il boot il BIOS usa la cache L2 come memoria temporanea perchè il controller RAM ancora non è inizializzato. Ci sono alcuni problemi con questo meccanismo. Il workaround elimina il problema. E' un problema solo al boot e di interesse solo per chi scrive BIOS.

344 NON Corretto sia nel C3 che nel D
Intermittent HyperTransport™ Link Training Failures
Description
The HyperTransport™ link training may fail at speeds greater than 2.0 GT/s.
Potential Effect on System
When exiting from S3, S4 or S5 state, the system may hang when a reset or LDTSTOP is applied and the link speed is greater than 2.0 GT/s. In addition, when F0x[18C:170][Ls2En] is set the system may hang exiting from LS2 link power state if the link speed is greater than 2.0 GT/s.
Suggested Workaround
System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. The bits should be set before the link frequency is changed from the cold reset value.
Fix Planned
No

In breve: problema elettrico sul link HTT durante le transizioni del risparmio energetico. Il workaround risolve il problema. Di interesse solo per chi scrive BIOS.

346 Corretto solo nel D (PRESENTE NEL C3)
System May Hang if Core Frequency is Even Divisor of
Northbridge Clock
Description
When one processor core is operating at a clock frequency that is higher than the Northbridge clock frequency, and another processor core is operating at a clock frequency that is an even divisor of the Northbridge clock frequency, the Northbridge may fail to complete a cache probe.
Potential Effect on System
System hang.
Suggested Workaround
System software should set F3x188[22] to 1b.
Fix Planned
Yes

In breve: blocco di sistema con frequenza clock dim uno dei core multiplo pari della frequenza NB. La soluzione è evitare, nei PState, alcune frequenze.

350 NON Corretto sia nel C3 che nel D
DRAM May Fail Training on Cold Reset
Description
The DRAM DQS DLL may not lock after PWROK is asserted, resulting in a DRAM training failure.
Potential Effect on System
The system may fail to boot.
Suggested Workaround
During DRAM controller (DCT) initialization, system software should perform the following workaround to every enabled DCT in the system:
1. Perform a dummy DRAM read to any address on any DIMM attached to the DCT.
2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.
3. Wait at least 300 nanoseconds.
4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C.
5. Wait at least 2 microseconds.
When exiting from the S4 or S5 state, apply the workaround immediately prior to the Receiver Enable Training. During resume from the S3 state, apply the workaround after F2x[1, 0]90[ExitSelfRef] has been cleared and prior to restoring the F2x[1, 0]9C registers.
Fix Planned
No

In breve: problema solo al BOOT. Il workaround risolve il problema. Di interesse solo per chi scrive BIOS.

352 Corretto solo nel D (PRESENTE NEL C3)
SYSCALL Instruction May Execute Incorrectly Due to Breakpoint
Description
A SYSCALL instruction will execute incorrectly and an incorrect debug exception will be taken when all of the following conditions are satisfied:
• An enabled instruction breakpoint address matches the RIP of the SYSCALL instruction.
• The processor is in 64-bit mode or compatibility mode.
• The instruction would not generate any other exception.
• SYSCALL Flag Mask Register[16] (MSRC000_0084[16]) is set to 1b.
• RFLAGS.RF is set to 1b.
Potential Effect on System
None expected during normal operation. Kernel debuggers may observe unpredictable system behavior.
Suggested Workaround
Operating system software should clear SYSCALL Flag Mask Register[16] (MSRC000_0084[16]) to 0b during initialization.
Fix Planned
Yes

In breve: deviazione dalle specifiche ma solo in fase di debugging. Di scarso interesse per gli utenti normali.

353 Corretto solo nel D (PRESENTE NEL C3)
SYSRET Instruction May Execute Incorrectly Due to Breakpoint
Description
A SYSRET instruction will execute incorrectly and an incorrect debug exception will be taken when all of the following conditions are satisfied:
• An enabled instruction breakpoint address matches the RIP of the SYSRET instruction.
• The processor is in 64-bit mode or compatibility mode.
• The instruction would not generate any other exception.
• R11[16] is cleared to 0b.
• RFLAGS.RF is set to 1b.
Potential Effect on System
None expected during normal operation. Kernel debuggers may observe unpredictable system behavior.
Suggested Workaround
Software should set R11[16] to 1b before executing the SYSRET instruction in 64-bit mode.
Fix Planned
Yes

In breve: deviazione dalle specifiche ma solo in fase di debugging. Di scarso interesse per gli utenti normali.

354 Corretto solo nel D (PRESENTE NEL C3)
HyperTransport™ Link Training Failure
Description
Some processors may fail HyperTransport™ link training at speeds greater than 2.0 GT/s. The link training failure may be intermittent.
Potential Effect on System
When exiting from S3, S4 or S5 state, the system may hang when a reset or LDTSTOP is applied and the link speed is greater than 2.0 GT/s. In addition, when F0x[18C:170][Ls2En] is set the system may hang exiting from LS2 link power state if the link speed is greater than 2.0 GT/s.
Suggested Workaround
System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. The bits should be set before the link frequency is changed from the cold reset value.
Fix Planned
Yes

In breve: problema elettrico sul link HTT durante le transizioni del risparmio energetico. Il workaround risolve il problema. Di interesse solo per chi scrive BIOS.

359 Corretto solo nel D (PRESENTE NEL C3)
MEMCLK is Not Provided for Minimum Specified Time Before CKE Assertion
Description
During hardware DDR2 device initialization, the processor does not provide a running MEMCLK for the specified minimum time of 200 us before CKE is asserted.
Potential Effect on System
No adverse effects have been observed. The processor does not initiate a DRAM access for over 200 us from the start of MEMCLK and the assertion of CKE. If a DDR2 DIMM is sensitive to this issue, the system may fail to boot.
Suggested Workaround
None required.
Fix Planned
Yes

In breve: problema solo al BOOT. Il workaround risolve il problema. Di interesse solo per gli scrittori di BIOS.

361 NON Corretto sia nel C3 che nel D
Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost
Description
A #DB exception occurring in guest mode may be discarded under the following conditions:
• A trap-type #DB exception is generated in guest mode during execution of an instruction with an interrupt shadow, and
• The instruction that generated the exception is immediately followed by an instruction resulting in #VMEXIT.
Potential Effect on System
None expected under normal conditions. Programs running under a hypervisor may not receive an expected #DB exception.
Suggested Workaround
None.
Fix Planned
No

In breve: in una macchina virtuale in alcune rare condizioni una trap di debug può essere persa. In condizioni normali nessun problema. Interessa solo chi fa debugging di software all'interno di una macchina virtuale.

362 Corretto nel C3 e D
Illegal Packet on HyperTransport™ Link May Prevent Warm Reset
Description
The processor may fail to drive external pins to their reset pattern when warm reset is asserted, and may fail to restart after warm reset is subsequently deasserted, when both of the following conditions
are satisfied:
• The processor has received an illegal packet from a non-coherent HyperTransport™ link with a specific encoding only used on coherent links. This packet may be detected near a warm reset as the processor may sample packets on the link for a brief time after warm reset is asserted. On some platforms, the conditions under which the processor may receive an illegal packet near a warm reset may not be observed. If link retry mode is enabled, this erratum applies only if the incoming illegal packet contains a valid CRC.
• One or more processor cores is in the C1 halt state with clocks ramped down. If C1 ACPI Power State Control Registers [CpuPrbEn] (F3x84[24]) = 1b, clocks are considered as ramped down for a processor core in the C1 halt state for any valid setting of F3x84[31:29] (ClkDivisor) other than 000b.
Potential Effect on System
System hang during a warm reset. This erratum does not impact cold reset or INIT.
Suggested Workaround
None required for platforms that do not observe this issue. For other platforms, platform BIOS should set a global SMI trap on any write to a port that could cause warm reset to assert, and then execute the write from within the SMI handler. This ensures that no cores have clocks ramped down when warm reset is asserted. This workaround is not effective for warm resets that are initiated without a software write to a port that can be trapped.
Fix Planned
Yes

In breve: blocco sul warm reset in particolari condizioni. Il wokaround risolve il problema. Di interesse solo per gli scrittori di BIOS.

372 NON Corretto sia nel C3 che nel D
Processor Read That Matches The Address of an Earlier Uncompleted Write May Be Incorrect
Description
Under highly specific and detailed internal timing conditions, processor data for a read may be corrupted when a read occurs that matches the address of an earlier uncompleted write or L3 eviction. This erratum applies only when both of the following conditions are satisfied on any processor node:
• DRAM controllers are in DCT link unganged mode ([DRAM Controller Select Low Register] F2x110[DctGangEn] = 0b).
• The Northbridge current operating frequency (COF) is less than 3 times the memory clock frequency.
Potential Effect on System
Unpredictable system behavior.
Suggested Workaround
On systems supporting DDR3-1333 or Northbridge P-state 1, and using DCT link unganged mode, system software should set MSRC001_001F[52:51] to 11b.
Fix Planned
No

In breve: in modalità unganged e con il clock NB minore del triplo della frequenza RAM, può verificarsi in rari casi un errore. Il workaround risolve il problema disabilitando qualcosa. Possibili cali prestazionali.

374 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
Processor Read From L3 Cache May Return Stale Data
Description
Under highly specific and detailed internal timing conditions, a processor read from the L3 cache may return stale data.
Potential Effect on System
Unpredictable system behavior due to incorrect read data.
Suggested Workaround
System software should set F3x1B8[18] to 1b.
Fix Planned
Yes

In breve: problema con la cache L3. Il workaround risolve il problema disabilitando qualcosa. Possibili cali prestazionali.

378 Corretto solo nel D (PRESENTE NEL C3)
Processor May Operate at Reduced Frequency
Description
When Product Information Register F3x1FC[31] is set, the reset values of the P-State Registers (MSRC001_00[68:64]) are not compliant with prior algorithms used to specify the P-state frequencies. Only one P-state register has bit 63 (PstateEn) set and the CPU frequency specified by this P-State register is below the maximum operating frequency for the processor.
Potential Effect on System
AM3 package processors may experience performance degradation when installed in an AM2r2 or AM3 platform.
Suggested Workaround
No workaround exists for AM2 platforms.
On AM2r2 and AM3 platforms, if F3x1FC[31] is set BIOS must follow the updated algorithm to write MSRC001_00[68:64] with corrected values, as documented in revision 3.23 or later versions of the BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 10h Processors, order# 31116.
Fix Planned
No

In breve: al reset in specifici casi il P-state più veloce può essere disabilitato. Il fix esiste per Am2+ e AM3+, ma non per AM2.

379 Corretto nel C3 e D
DDR3-1333 Configurations with Two DIMMs per Channel May Experience Unreliable Operation
Description
In systems with more than one DDR3-1333 unbuffered DIMM on a channel, the processor memory subsystem may exhibit unreliable operation over the allowable VDDIO voltage range. This erratum does not apply to DDR3-1333 configurations when only one DIMM per channel is populated.
Potential Effect on System
Memory system failure leading to unpredictable system behavior.
Suggested Workaround
In a configuration where two unbuffered DDR3-1333 DIMMs are populated on one channel, BIOS should derate DDR3-1333 system memory to 533 MHz operation (DDR3-1066) by setting the DRAM Configuration High Register[MemClkFreq] (F2x[1, 0]94[2:0]) to 100b and adjusting memory subsystem timing parameters accordingly.
Fix Planned
Yes

In breve: questa è la mitica instabilità RAM a 1333 MHz e 4 moduli. La soluzione è portarla a 1066, anche se è stato verificato che overvoltando le RAM si risolve il problema.

382 Corretto solo nel D (PRESENTE NEL C3)
L3 Cache Index Disable Cannot Be Modified After L3 Cache is Enabled
Description
The processor does not support the disabling of L3 locations through use of the L3 Cache Index Disable Registers (F3x[1C0, 1BC]) after the cache subsystem has been enabled through CR0.
Potential Effect on System
If software modifies F3x[1C0, 1BC] after the L3 cache has been enabled through CR0, unpredictable system behavior may result.
Suggested Workaround
None.
Fix Planned
Yes

In breve: se durante il funzionamento si rileva un malfunzionamento della cache L3, il processore dovrebbe supportare la disabilitazione di parti della cache L3 al volo. Questo meccanismo non funziona sugli step indicati. Se si prova a disabilitare la cache L3 durante il funzionamento, si possono avere malfunzionamenti.

384 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
DRAM Prefetch May Cause System Hang When Probe Filter is Enabled
Description
When the processor is accessing memory with the probe filter and DRAM prefetch enabled, a DRAM prefetch may not complete.
Potential Effect on System
System hang.
Suggested Workaround
If the probe filter is enabled, system software should program MSRC001_001F[20] to 1b.
Fix Planned
Yes

In breve: il prefetch non funziona con il probe filter (HT assist) abilitato. Il workaround è disabilitare il prefetching. Attualmente il bug interessa solo sistemi Instambul con 4 o 8 socket (su sistemi 1p e 2p abilitare l'HT assist non è nbecessario). Risolto questo bug ci si dovrebbe aspettere ulteriori miglioramenti delle prestazioni (già spettacolari) dell'instambul...

385 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
Processor May Report Incorrect Address For an L3 Cache Error Machine Check
Description
The processor may report an incorrect address at NB Machine Check Address Register MSR0000_0412 when executing a machine check for an L3 cache error. In addition, when disabling an L3 cache index by writing to L3 Cache Index Disable Registers F3x[1C0, 1BC] [Index], the processor may not disable the intended L3 cache index.
Potential Effect on System
Operating system software may take inappropriate action due to an incorrectly reported L3 cache error.
Suggested Workaround
System software should program F3x1B8[23] to 1b before enabling the L3 cache through CR0[30] (CD).
Fix Planned
No

In breve: quando c'è un errore sulla cache L3, potrebbe essere riportato l'indirizzo sbagliato. Il workaround disabilita qualcosa.

386 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
HyperTransport™ Link in Retry Mode That Receives Repeated Invalid Packets May Cause MCA Exception
Description
Under highly specific and detailed internal timing conditions, a HyperTransport™ link in retry mode that receives repeated invalid packets in a specific sequence may cause the processor to generate a link data buffer overflow MCA exception. This erratum applies only when a link is configured as 16-bit ganged and the Northbridge current operating frequency is less than the link clock frequency.
Potential Effect on System
System hang. A link data buffer overflow MCA exception will also be reported.
Suggested Workaround System software should program the Link Base Channel Buffer Count Registers F0x[F0, D0, B0, 90][27:25] (FreeData) to 000b to disable all free list link data buffers. To maximize system performance when applying this workaround on NFCM coherent links, system software should modify the settings for F0x[F0, D0, B0, 90] as specified in the BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 10h Processors, order# 31116, per the following table:
Fix Planned
Yes

In breve: in specifiche condizioni e quando il clock HT è superiore al clock NB (possibile SOLO con lo step D) possono verificarsi problemi. Il workaround disabilita qualcosa e i suggerimenti limitano la perdita di prestazioni.

388 NON Corretto sia nel C3 che nel D
L3 Cache Scrubbing Does Not Bypass Disabled L3 Cache Locations
Description
The processor does not discontinue scrubbing L3 cache locations that are disabled through the L3 Cache Index Disable Registers F3x[1C0, 1BC].
Potential Effect on System
ECC errors that occur when scrubbing disabled L3 cache locations can generate unexpected machine check exceptions.
Suggested Workaround
System software should program Scrub Rate Control Register F3x58[28:24] (L3Scrub) to 00000b before disabling any L3 cache locations. This workaround should not be applied when all L3 cache locations are enabled.
Fix Planned
Yes

In breve: il meccanismo di test continuo della cache L3, testa anche la cache disabilitata per errori. Quindi potrebbe essere riportato un errore su una cache già disabilitata. Il workaround evita questo problema.

389 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
HyperTransport™ Link in Retry Mode May Consume Link Packet Buffer Incorrectly
Description
Under highly specific and detailed internal timing conditions, a coherent HyperTransport™ link in retry mode that receives an invalid per-packet CRC may cause the processor to incorrectly consume a link packet buffer during link retry. This erratum applies only when F0x150[11:9] (HtRetryCrcDatIns) is set to a value other than 000b.
Potential Effect on System
System hang.
Suggested Workaround
When CPUID Fn0000_0001_EAX[7:4] (Model) < 8, no workaround is required. For system developers that wish to provide a workaround for this event, system software may clear F0x150[11:9] (HtRetryCrcDatIns) to 000b.
System software should clear F0x150[11:9] (HtRetryCrcDatIns) to 000b for all other affected silicon revisions.
Fix Planned
Yes

In breve: in rari casi su un errore su un link HT coerente (quindi solo in sistemi multisocket) non è risolto correttamente. Il workaround risolve il problema.

391 NON Corretto sia nel C3 che nel D
HyperTransport™ Link RTT and RON Specification Violations
Description
The RTT and RON specifications of the HyperTransport™ link may be violated on some lanes.
Potential Effect on System
These violations do not result in any functional failures on HyperTransport™ links.
Suggested Workaround
None.
Fix Planned
No

In breve: lieve problema eletrico sui link HTT senza conseguenze.

395 Corretto nel C3 e D
Incorrect Data Masking in Ganged DRAM Mode
Description
The DRAM controller may apply incorrect DRAM data masks when operating in ganged mode (DRAM Controller Select Low Register[DctGangEn] (F2x110[4]) is set to 1b).
Potential Effect on System
Unpredictable system behavior.
Suggested Workaround
The DRAM controllers should only be configured in the unganged mode. BIOS should not set DRAM Controller Select Low Register[DctGangEn] (F2x110[4]). When only a single DCT is in use, DctGangEn is always zero.
Fix Planned
Yes

In breve: problema in ganged mode.

396 NON Corretto sia nel C3 che nel D
VLDT Maximum Current Specification Exceeded at HyperTransport™ Link Transfer Rates Up to 2.0 GT/s
Description
At HyperTransport™ link transfer rates up to 2.0 GT/s, VLDT maximum current (ILDT) may exceed the specified 500 mA per link limit.
Potential Effect on System
The processor may exceed the design of the power subsystem, resulting in over-current conditions that can lead to a shutdown or voltage droop.
Suggested Workaround
For platforms that utilize Gen1 link transfer rates less than or equal to 2.0 GT/s, refer to the following documents for updated VLDT current specifications:
• AMD Family 10h Server and Workstation Processor Power and Thermal Datasheet, order #43374 revision 3.07 or later
• AMD Family 10h Desktop Processor Power and Thermal Datasheet, order #43375 revision 3.33 or later
Fix Planned
No

In breve: lieve problema elettrico senza conseguenze su link HTT.

397 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
VLDT Maximum Current Specification Exceeded on HyperTransport™ Links in Retry Mode
Description
HyperTransport™ links in retry mode may exceed the 1.4 A per link VLDT maximum current (ILDT) specification.
Potential Effect on System
The processor may exceed the design of the power subsystem, resulting in over-current conditions that can lead to a shutdown or voltage droop.
Suggested Workaround
Refer to the following document for updated VLDT current specifications:
• AMD Family 10h Server and Workstation Processor Power and Thermal Datasheet, order #43374 revision 3.04 or later
Fix Planned
No

In breve: lieve problema elettrico senza conseguenze su link HTT.

398 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
HyperTransport™ Links In Retry Mode May Experience High Bit Error Rate At Specific Link and Northbridge Clock Frequencies
Description
The processor HyperTransport™ link transmit FIFOs may underflow, resulting in bit errors. This erratum only applies when all of the following conditions are satisfied:
• Links are in retry mode.
• The HyperTransport link clock frequency is greater than the Northbridge clock frequency.
• The HyperTransport link clock frequency is an odd multiple of 200 MHz.
• LDTSTOP# has not been asserted since the last warm reset.
Potential Effect on System
The link may fail to train due to multiple bit errors, or experience excessive retries. This behavior may be intermittent.
Suggested Workaround
At link and Northbridge frequency settings where the erratum applies, system software should subtract 0010b from the four bit value programmed into Link FIFO Read Pointer Optimization Registers F4x1[9C, 94, 8C, 84]_x[DF, CF][7:4] (XmtRdPtr). If the result of the subtraction is negative, truncate it to four bits of precision.
Fix Planned
Yes

In breve: per clock HT superiori al clock NB (possibile SOLO sullo step D) e moltiplicatori DISPARI del link HTT e con il retry abilitato, possono verificarsi alti tassi di errore di trasmissione. Il workaround è usare solo moltiplicatori PARI per i link HTT. Non grave.

400 NON Corretto sia nel C3 che nel D
APIC Timer Interrupt Does Not Occur in Processor C-States
Description
An APIC timer interrupt that becomes pending in low-power states C1e or C3 will not cause the processor to enter the C0 state even if the interrupt is enabled by Timer Local Vector Table Entry[Mask], APIC320[16]). APIC timer functionality is otherwise unaffected.
Potential Effect on System
System hang may occur provided that the operating system has not configured another interrupt source. APIC timer interrupts may be delayed or, when the APIC timer is configured in rollover mode (APIC320[17]), the APIC timer may roll over multiple times in the low-power state with only one
interrupt presented after the processor resumes. The standard use of the APIC timer does not make this effect significant.
Suggested Workaround
Operating system software should enable another source of timer interrupts, such as the High Precision Event Timer, before it enters the C1 state by executing the HALT instruction and C1e is enabled through Interrupt Pending and CMP-Halt Register[C1eOnCmpHalt or SmiOnCmpHalt] (MSRC001_0055[28:27] are not 00b). For purposes of determining if C1e is enabled, the operating system should not sample MSRC001_0055 until after ACPI has been enabled. Operating system software should enable another source of timer interrupts, such as the High Precision Event Timer, when the processor enters the C3 state. It is possible for the system to implement a hardware fix to C1e mode on some processor revisions and some packages. This is indicated by OSVW[1] and no workaround is necessary when
OSVW_Length >= 2 and OSVW[1] is zero. An operating system workaround for C3 mode is always necessary, regardless of the setting of OSVW[1].
Fix Planned
C1e state: Yes
C3 state: No

In breve: problemi con le interrupt in risparmio energetico se si usa solo il timer APIC per le interruzioni. Il workaround risolve il problema.

407 Corretto solo nel D (PRESENTE NEL C3)
System May Hang Due to Stalled Probe Data Transfer
Description
Under highly detailed and specific internal timing conditions, a processor that has one or more processor cores in a cache-flushed state following a C1e exit, and one or more cores executing in C0 state, may not complete a data transfer for a probe.
Potential Effect on System
System hang.
Suggested Workaround
Contact your AMD representative for information on a BIOS update. This workaround requires that Clock Power/Timing Control 2 Register[CacheFlushOnHaltTmr] (F3xDC[25:19]) is greater than 01h, which is true under normal circumstances.
Fix Planned
Yes

In breve: in alcune circostanza in cui i core sono in risparmio energetico con la cache disabilitata (C1e), il processore si può bloccare nel probing di quei core. Solo se un registro è impostato in una data maniera, che in circostanze normali non è così...





In definitiva: lo step C3 corregge alcuni bugs. Lo step D ne corregge ancora altri, anche se ne introduce nuovi dovuti alle nuove funzionalità introdotte: probe filter/HT assist (solo in configurazioni server 4p e 8p) e HT link più veloce del NB clock...

Lo step D a mio avviso è meglio del C3... Chissà quando lo vedremo...

[bjt2]

Originariamente inviato da capitan_crasy

Per dirti la verità la cosa non mi dispiace affatto...
Comunque ecco il link del documento sul BIOS and Kernel Developer’s Guide (BKDG) aggiornato al 9 settembre 2009...
Clicca qui...

Qui mi devi dare un bel po' di tempo per leggerlo...

[Vash_85]

Grande bjt2... Scommetto che negli altri tread delle cpu ce lo invidiano tutti

[capitan_crasy]

Originariamente inviato da bjt2

Quel documento comprende anche lo step D...

edit

Lo step D a mio avviso è meglio del C3... Chissà quando lo vedremo...

Originariamente inviato da bjt2

Qui mi devi dare un bel po' di tempo per leggerlo...

Così avrò più tempo per preparare la nuova GIF in tuo onore!!!

[bjt2]

Originariamente inviato da capitan_crasy

Così avrò più tempo per preparare la nuova GIF in tuo onore!!!

Troppo buono...

Comunque ho iniziato a dare una occhiata al 31116...
Se trovo qualche cosa interessante, la posto...

[Pihippo]

Originariamente inviato da bjt2

Quel documento comprende anche lo step D...

Ecco un riassunto degli errata:

Errata corretti nel C3 e nel D:
362,379,395

Errata corretti solo nello step D (PRESENTI ANCORA NELLO STEP C3):
346,352,353,354,359,378,382,407

Errata ancora non corretti nello step C3 e D:
327,343,344,350,361,372,388,391,396,400

Errata nuovi dello step D (NON PRESENTI NEGLI STEP PRECEDENTI):
374,384,385,386,389,397,398



Nel dettaglio:

327 NON Corretto sia nel C3 che nel D
HyperTransport™ Link RTT Specification Violation
Description
The RTT specification for the HyperTransport™ link may be violated on some processor revisions.
Potential Effect on System
These violations do not result in any other HyperTransport™ link electrical specification violations. There are no known functional failures related to this problem.
Suggested Workaround
BIOS should set the Link Phy Impedance Register[RttCtl] (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and Link Phy Impedance Register[RttIndex] (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b.
Fix Planned
Yes

In breve: probelma elettrico sul link HTT che sembra senza conseguenze.

343 NON Corretto sia nel C3 che nel D
Eviction May Occur When Using L2 Cache as General Storage During Boot
Description
When system software is using the L2 cache as general storage before memory initialization, the processor may determine during speculative execution that data destined for the instruction cache is dirty. The processor will then evict these cache lines, resulting in lost data.
Potential Effect on System
System software using L2 cache as general storage before memory initialization may experience unpredictable system behavior.
Suggested Workaround
System software should set MSRC001_102A[35] to 1b prior to using L2 cache as general storage during boot. System software should clear MSRC001_102A[35] to 0b after the L2 cache is no longer used as general storage.
Fix Planned
No

In breve: durante il boot il BIOS usa la cache L2 come memoria temporanea perchè il controller RAM ancora non è inizializzato. Ci sono alcuni problemi con questo meccanismo. Il workaround elimina il problema. E' un problema solo al boot e di interesse solo per chi scrive BIOS.

344 NON Corretto sia nel C3 che nel D
Intermittent HyperTransport™ Link Training Failures
Description
The HyperTransport™ link training may fail at speeds greater than 2.0 GT/s.
Potential Effect on System
When exiting from S3, S4 or S5 state, the system may hang when a reset or LDTSTOP is applied and the link speed is greater than 2.0 GT/s. In addition, when F0x[18C:170][Ls2En] is set the system may hang exiting from LS2 link power state if the link speed is greater than 2.0 GT/s.
Suggested Workaround
System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. The bits should be set before the link frequency is changed from the cold reset value.
Fix Planned
No

In breve: problema elettrico sul link HTT durante le transizioni del risparmio energetico. Il workaround risolve il problema. Di interesse solo per chi scrive BIOS.

346 Corretto solo nel D (PRESENTE NEL C3)
System May Hang if Core Frequency is Even Divisor of
Northbridge Clock
Description
When one processor core is operating at a clock frequency that is higher than the Northbridge clock frequency, and another processor core is operating at a clock frequency that is an even divisor of the Northbridge clock frequency, the Northbridge may fail to complete a cache probe.
Potential Effect on System
System hang.
Suggested Workaround
System software should set F3x188[22] to 1b.
Fix Planned
Yes

In breve: blocco di sistema con frequenza clock dim uno dei core multiplo pari della frequenza NB. La soluzione è evitare, nei PState, alcune frequenze.

350 NON Corretto sia nel C3 che nel D
DRAM May Fail Training on Cold Reset
Description
The DRAM DQS DLL may not lock after PWROK is asserted, resulting in a DRAM training failure.
Potential Effect on System
The system may fail to boot.
Suggested Workaround
During DRAM controller (DCT) initialization, system software should perform the following workaround to every enabled DCT in the system:
1. Perform a dummy DRAM read to any address on any DIMM attached to the DCT.
2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.
3. Wait at least 300 nanoseconds.
4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C.
5. Wait at least 2 microseconds.
When exiting from the S4 or S5 state, apply the workaround immediately prior to the Receiver Enable Training. During resume from the S3 state, apply the workaround after F2x[1, 0]90[ExitSelfRef] has been cleared and prior to restoring the F2x[1, 0]9C registers.
Fix Planned
No

In breve: problema solo al BOOT. Il workaround risolve il problema. Di interesse solo per chi scrive BIOS.

352 Corretto solo nel D (PRESENTE NEL C3)
SYSCALL Instruction May Execute Incorrectly Due to Breakpoint
Description
A SYSCALL instruction will execute incorrectly and an incorrect debug exception will be taken when all of the following conditions are satisfied:
• An enabled instruction breakpoint address matches the RIP of the SYSCALL instruction.
• The processor is in 64-bit mode or compatibility mode.
• The instruction would not generate any other exception.
• SYSCALL Flag Mask Register[16] (MSRC000_0084[16]) is set to 1b.
• RFLAGS.RF is set to 1b.
Potential Effect on System
None expected during normal operation. Kernel debuggers may observe unpredictable system behavior.
Suggested Workaround
Operating system software should clear SYSCALL Flag Mask Register[16] (MSRC000_0084[16]) to 0b during initialization.
Fix Planned
Yes

In breve: deviazione dalle specifiche ma solo in fase di debugging. Di scarso interesse per gli utenti normali.

353 Corretto solo nel D (PRESENTE NEL C3)
SYSRET Instruction May Execute Incorrectly Due to Breakpoint
Description
A SYSRET instruction will execute incorrectly and an incorrect debug exception will be taken when all of the following conditions are satisfied:
• An enabled instruction breakpoint address matches the RIP of the SYSRET instruction.
• The processor is in 64-bit mode or compatibility mode.
• The instruction would not generate any other exception.
• R11[16] is cleared to 0b.
• RFLAGS.RF is set to 1b.
Potential Effect on System
None expected during normal operation. Kernel debuggers may observe unpredictable system behavior.
Suggested Workaround
Software should set R11[16] to 1b before executing the SYSRET instruction in 64-bit mode.
Fix Planned
Yes

In breve: deviazione dalle specifiche ma solo in fase di debugging. Di scarso interesse per gli utenti normali.

354 Corretto solo nel D (PRESENTE NEL C3)
HyperTransport™ Link Training Failure
Description
Some processors may fail HyperTransport™ link training at speeds greater than 2.0 GT/s. The link training failure may be intermittent.
Potential Effect on System
When exiting from S3, S4 or S5 state, the system may hang when a reset or LDTSTOP is applied and the link speed is greater than 2.0 GT/s. In addition, when F0x[18C:170][Ls2En] is set the system may hang exiting from LS2 link power state if the link speed is greater than 2.0 GT/s.
Suggested Workaround
System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. The bits should be set before the link frequency is changed from the cold reset value.
Fix Planned
Yes

In breve: problema elettrico sul link HTT durante le transizioni del risparmio energetico. Il workaround risolve il problema. Di interesse solo per chi scrive BIOS.

359 Corretto solo nel D (PRESENTE NEL C3)
MEMCLK is Not Provided for Minimum Specified Time Before CKE Assertion
Description
During hardware DDR2 device initialization, the processor does not provide a running MEMCLK for the specified minimum time of 200 us before CKE is asserted.
Potential Effect on System
No adverse effects have been observed. The processor does not initiate a DRAM access for over 200 us from the start of MEMCLK and the assertion of CKE. If a DDR2 DIMM is sensitive to this issue, the system may fail to boot.
Suggested Workaround
None required.
Fix Planned
Yes

In breve: problema solo al BOOT. Il workaround risolve il problema. Di interesse solo per gli scrittori di BIOS.

361 NON Corretto sia nel C3 che nel D
Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost
Description
A #DB exception occurring in guest mode may be discarded under the following conditions:
• A trap-type #DB exception is generated in guest mode during execution of an instruction with an interrupt shadow, and
• The instruction that generated the exception is immediately followed by an instruction resulting in #VMEXIT.
Potential Effect on System
None expected under normal conditions. Programs running under a hypervisor may not receive an expected #DB exception.
Suggested Workaround
None.
Fix Planned
No

In breve: in una macchina virtuale in alcune rare condizioni una trap di debug può essere persa. In condizioni normali nessun problema. Interessa solo chi fa debugging di software all'interno di una macchina virtuale.

362 Corretto nel C3 e D
Illegal Packet on HyperTransport™ Link May Prevent Warm Reset
Description
The processor may fail to drive external pins to their reset pattern when warm reset is asserted, and may fail to restart after warm reset is subsequently deasserted, when both of the following conditions
are satisfied:
• The processor has received an illegal packet from a non-coherent HyperTransport™ link with a specific encoding only used on coherent links. This packet may be detected near a warm reset as the processor may sample packets on the link for a brief time after warm reset is asserted. On some platforms, the conditions under which the processor may receive an illegal packet near a warm reset may not be observed. If link retry mode is enabled, this erratum applies only if the incoming illegal packet contains a valid CRC.
• One or more processor cores is in the C1 halt state with clocks ramped down. If C1 ACPI Power State Control Registers [CpuPrbEn] (F3x84[24]) = 1b, clocks are considered as ramped down for a processor core in the C1 halt state for any valid setting of F3x84[31:29] (ClkDivisor) other than 000b.
Potential Effect on System
System hang during a warm reset. This erratum does not impact cold reset or INIT.
Suggested Workaround
None required for platforms that do not observe this issue. For other platforms, platform BIOS should set a global SMI trap on any write to a port that could cause warm reset to assert, and then execute the write from within the SMI handler. This ensures that no cores have clocks ramped down when warm reset is asserted. This workaround is not effective for warm resets that are initiated without a software write to a port that can be trapped.
Fix Planned
Yes

In breve: blocco sul warm reset in particolari condizioni. Il wokaround risolve il problema. Di interesse solo per gli scrittori di BIOS.

372 NON Corretto sia nel C3 che nel D
Processor Read That Matches The Address of an Earlier Uncompleted Write May Be Incorrect
Description
Under highly specific and detailed internal timing conditions, processor data for a read may be corrupted when a read occurs that matches the address of an earlier uncompleted write or L3 eviction. This erratum applies only when both of the following conditions are satisfied on any processor node:
• DRAM controllers are in DCT link unganged mode ([DRAM Controller Select Low Register] F2x110[DctGangEn] = 0b).
• The Northbridge current operating frequency (COF) is less than 3 times the memory clock frequency.
Potential Effect on System
Unpredictable system behavior.
Suggested Workaround
On systems supporting DDR3-1333 or Northbridge P-state 1, and using DCT link unganged mode, system software should set MSRC001_001F[52:51] to 11b.
Fix Planned
No

In breve: in modalità unganged e con il clock NB minore del triplo della frequenza RAM, può verificarsi in rari casi un errore. Il workaround risolve il problema disabilitando qualcosa. Possibili cali prestazionali.

374 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
Processor Read From L3 Cache May Return Stale Data
Description
Under highly specific and detailed internal timing conditions, a processor read from the L3 cache may return stale data.
Potential Effect on System
Unpredictable system behavior due to incorrect read data.
Suggested Workaround
System software should set F3x1B8[18] to 1b.
Fix Planned
Yes

In breve: problema con la cache L3. Il workaround risolve il problema disabilitando qualcosa. Possibili cali prestazionali.

378 Corretto solo nel D (PRESENTE NEL C3)
Processor May Operate at Reduced Frequency
Description
When Product Information Register F3x1FC[31] is set, the reset values of the P-State Registers (MSRC001_00[68:64]) are not compliant with prior algorithms used to specify the P-state frequencies. Only one P-state register has bit 63 (PstateEn) set and the CPU frequency specified by this P-State register is below the maximum operating frequency for the processor.
Potential Effect on System
AM3 package processors may experience performance degradation when installed in an AM2r2 or AM3 platform.
Suggested Workaround
No workaround exists for AM2 platforms.
On AM2r2 and AM3 platforms, if F3x1FC[31] is set BIOS must follow the updated algorithm to write MSRC001_00[68:64] with corrected values, as documented in revision 3.23 or later versions of the BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 10h Processors, order# 31116.
Fix Planned
No

In breve: al reset in specifici casi il P-state più veloce può essere disabilitato. Il fix esiste per Am2+ e AM3+, ma non per AM2.

379 Corretto nel C3 e D
DDR3-1333 Configurations with Two DIMMs per Channel May Experience Unreliable Operation
Description
In systems with more than one DDR3-1333 unbuffered DIMM on a channel, the processor memory subsystem may exhibit unreliable operation over the allowable VDDIO voltage range. This erratum does not apply to DDR3-1333 configurations when only one DIMM per channel is populated.
Potential Effect on System
Memory system failure leading to unpredictable system behavior.
Suggested Workaround
In a configuration where two unbuffered DDR3-1333 DIMMs are populated on one channel, BIOS should derate DDR3-1333 system memory to 533 MHz operation (DDR3-1066) by setting the DRAM Configuration High Register[MemClkFreq] (F2x[1, 0]94[2:0]) to 100b and adjusting memory subsystem timing parameters accordingly.
Fix Planned
Yes

In breve: questa è la mitica instabilità RAM a 1333 MHz e 4 moduli. La soluzione è portarla a 1066, anche se è stato verificato che overvoltando le RAM si risolve il problema.

382 Corretto solo nel D (PRESENTE NEL C3)
L3 Cache Index Disable Cannot Be Modified After L3 Cache is Enabled
Description
The processor does not support the disabling of L3 locations through use of the L3 Cache Index Disable Registers (F3x[1C0, 1BC]) after the cache subsystem has been enabled through CR0.
Potential Effect on System
If software modifies F3x[1C0, 1BC] after the L3 cache has been enabled through CR0, unpredictable system behavior may result.
Suggested Workaround
None.
Fix Planned
Yes

In breve: se durante il funzionamento si rileva un malfunzionamento della cache L3, il processore dovrebbe supportare la disabilitazione di parti della cache L3 al volo. Questo meccanismo non funziona sugli step indicati. Se si prova a disabilitare la cache L3 durante il funzionamento, si possono avere malfunzionamenti.

384 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
DRAM Prefetch May Cause System Hang When Probe Filter is Enabled
Description
When the processor is accessing memory with the probe filter and DRAM prefetch enabled, a DRAM prefetch may not complete.
Potential Effect on System
System hang.
Suggested Workaround
If the probe filter is enabled, system software should program MSRC001_001F[20] to 1b.
Fix Planned
Yes

In breve: il prefetch non funziona con il probe filter (HT assist) abilitato. Il workaround è disabilitare il prefetching. Attualmente il bug interessa solo sistemi Instambul con 4 o 8 socket (su sistemi 1p e 2p abilitare l'HT assist non è nbecessario). Risolto questo bug ci si dovrebbe aspettere ulteriori miglioramenti delle prestazioni (già spettacolari) dell'instambul...

385 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
Processor May Report Incorrect Address For an L3 Cache Error Machine Check
Description
The processor may report an incorrect address at NB Machine Check Address Register MSR0000_0412 when executing a machine check for an L3 cache error. In addition, when disabling an L3 cache index by writing to L3 Cache Index Disable Registers F3x[1C0, 1BC] [Index], the processor may not disable the intended L3 cache index.
Potential Effect on System
Operating system software may take inappropriate action due to an incorrectly reported L3 cache error.
Suggested Workaround
System software should program F3x1B8[23] to 1b before enabling the L3 cache through CR0[30] (CD).
Fix Planned
No

In breve: quando c'è un errore sulla cache L3, potrebbe essere riportato l'indirizzo sbagliato. Il workaround disabilita qualcosa.

386 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
HyperTransport™ Link in Retry Mode That Receives Repeated Invalid Packets May Cause MCA Exception
Description
Under highly specific and detailed internal timing conditions, a HyperTransport™ link in retry mode that receives repeated invalid packets in a specific sequence may cause the processor to generate a link data buffer overflow MCA exception. This erratum applies only when a link is configured as 16-bit ganged and the Northbridge current operating frequency is less than the link clock frequency.
Potential Effect on System
System hang. A link data buffer overflow MCA exception will also be reported.
Suggested Workaround System software should program the Link Base Channel Buffer Count Registers F0x[F0, D0, B0, 90][27:25] (FreeData) to 000b to disable all free list link data buffers. To maximize system performance when applying this workaround on NFCM coherent links, system software should modify the settings for F0x[F0, D0, B0, 90] as specified in the BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 10h Processors, order# 31116, per the following table:
Fix Planned
Yes

In breve: in specifiche condizioni e quando il clock HT è superiore al clock NB (possibile SOLO con lo step D) possono verificarsi problemi. Il workaround disabilita qualcosa e i suggerimenti limitano la perdita di prestazioni.

388 NON Corretto sia nel C3 che nel D
L3 Cache Scrubbing Does Not Bypass Disabled L3 Cache Locations
Description
The processor does not discontinue scrubbing L3 cache locations that are disabled through the L3 Cache Index Disable Registers F3x[1C0, 1BC].
Potential Effect on System
ECC errors that occur when scrubbing disabled L3 cache locations can generate unexpected machine check exceptions.
Suggested Workaround
System software should program Scrub Rate Control Register F3x58[28:24] (L3Scrub) to 00000b before disabling any L3 cache locations. This workaround should not be applied when all L3 cache locations are enabled.
Fix Planned
Yes

In breve: il meccanismo di test continuo della cache L3, testa anche la cache disabilitata per errori. Quindi potrebbe essere riportato un errore su una cache già disabilitata. Il workaround evita questo problema.

389 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
HyperTransport™ Link in Retry Mode May Consume Link Packet Buffer Incorrectly
Description
Under highly specific and detailed internal timing conditions, a coherent HyperTransport™ link in retry mode that receives an invalid per-packet CRC may cause the processor to incorrectly consume a link packet buffer during link retry. This erratum applies only when F0x150[11:9] (HtRetryCrcDatIns) is set to a value other than 000b.
Potential Effect on System
System hang.
Suggested Workaround
When CPUID Fn0000_0001_EAX[7:4] (Model) < 8, no workaround is required. For system developers that wish to provide a workaround for this event, system software may clear F0x150[11:9] (HtRetryCrcDatIns) to 000b.
System software should clear F0x150[11:9] (HtRetryCrcDatIns) to 000b for all other affected silicon revisions.
Fix Planned
Yes

In breve: in rari casi su un errore su un link HT coerente (quindi solo in sistemi multisocket) non è risolto correttamente. Il workaround risolve il problema.

391 NON Corretto sia nel C3 che nel D
HyperTransport™ Link RTT and RON Specification Violations
Description
The RTT and RON specifications of the HyperTransport™ link may be violated on some lanes.
Potential Effect on System
These violations do not result in any functional failures on HyperTransport™ links.
Suggested Workaround
None.
Fix Planned
No

In breve: lieve problema eletrico sui link HTT senza conseguenze.

395 Corretto nel C3 e D
Incorrect Data Masking in Ganged DRAM Mode
Description
The DRAM controller may apply incorrect DRAM data masks when operating in ganged mode (DRAM Controller Select Low Register[DctGangEn] (F2x110[4]) is set to 1b).
Potential Effect on System
Unpredictable system behavior.
Suggested Workaround
The DRAM controllers should only be configured in the unganged mode. BIOS should not set DRAM Controller Select Low Register[DctGangEn] (F2x110[4]). When only a single DCT is in use, DctGangEn is always zero.
Fix Planned
Yes

In breve: problema in ganged mode.

396 NON Corretto sia nel C3 che nel D
VLDT Maximum Current Specification Exceeded at HyperTransport™ Link Transfer Rates Up to 2.0 GT/s
Description
At HyperTransport™ link transfer rates up to 2.0 GT/s, VLDT maximum current (ILDT) may exceed the specified 500 mA per link limit.
Potential Effect on System
The processor may exceed the design of the power subsystem, resulting in over-current conditions that can lead to a shutdown or voltage droop.
Suggested Workaround
For platforms that utilize Gen1 link transfer rates less than or equal to 2.0 GT/s, refer to the following documents for updated VLDT current specifications:
• AMD Family 10h Server and Workstation Processor Power and Thermal Datasheet, order #43374 revision 3.07 or later
• AMD Family 10h Desktop Processor Power and Thermal Datasheet, order #43375 revision 3.33 or later
Fix Planned
No

In breve: lieve problema elettrico senza conseguenze su link HTT.

397 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
VLDT Maximum Current Specification Exceeded on HyperTransport™ Links in Retry Mode
Description
HyperTransport™ links in retry mode may exceed the 1.4 A per link VLDT maximum current (ILDT) specification.
Potential Effect on System
The processor may exceed the design of the power subsystem, resulting in over-current conditions that can lead to a shutdown or voltage droop.
Suggested Workaround
Refer to the following document for updated VLDT current specifications:
• AMD Family 10h Server and Workstation Processor Power and Thermal Datasheet, order #43374 revision 3.04 or later
Fix Planned
No

In breve: lieve problema elettrico senza conseguenze su link HTT.

398 CORRETTO NEL C2 e C3 e NON CORRETTO NELLO STEP D
HyperTransport™ Links In Retry Mode May Experience High Bit Error Rate At Specific Link and Northbridge Clock Frequencies
Description
The processor HyperTransport™ link transmit FIFOs may underflow, resulting in bit errors. This erratum only applies when all of the following conditions are satisfied:
• Links are in retry mode.
• The HyperTransport link clock frequency is greater than the Northbridge clock frequency.
• The HyperTransport link clock frequency is an odd multiple of 200 MHz.
• LDTSTOP# has not been asserted since the last warm reset.
Potential Effect on System
The link may fail to train due to multiple bit errors, or experience excessive retries. This behavior may be intermittent.
Suggested Workaround
At link and Northbridge frequency settings where the erratum applies, system software should subtract 0010b from the four bit value programmed into Link FIFO Read Pointer Optimization Registers F4x1[9C, 94, 8C, 84]_x[DF, CF][7:4] (XmtRdPtr). If the result of the subtraction is negative, truncate it to four bits of precision.
Fix Planned
Yes

In breve: per clock HT superiori al clock NB (possibile SOLO sullo step D) e moltiplicatori DISPARI del link HTT e con il retry abilitato, possono verificarsi alti tassi di errore di trasmissione. Il workaround è usare solo moltiplicatori PARI per i link HTT. Non grave.

400 NON Corretto sia nel C3 che nel D
APIC Timer Interrupt Does Not Occur in Processor C-States
Description
An APIC timer interrupt that becomes pending in low-power states C1e or C3 will not cause the processor to enter the C0 state even if the interrupt is enabled by Timer Local Vector Table Entry[Mask], APIC320[16]). APIC timer functionality is otherwise unaffected.
Potential Effect on System
System hang may occur provided that the operating system has not configured another interrupt source. APIC timer interrupts may be delayed or, when the APIC timer is configured in rollover mode (APIC320[17]), the APIC timer may roll over multiple times in the low-power state with only one
interrupt presented after the processor resumes. The standard use of the APIC timer does not make this effect significant.
Suggested Workaround
Operating system software should enable another source of timer interrupts, such as the High Precision Event Timer, before it enters the C1 state by executing the HALT instruction and C1e is enabled through Interrupt Pending and CMP-Halt Register[C1eOnCmpHalt or SmiOnCmpHalt] (MSRC001_0055[28:27] are not 00b). For purposes of determining if C1e is enabled, the operating system should not sample MSRC001_0055 until after ACPI has been enabled. Operating system software should enable another source of timer interrupts, such as the High Precision Event Timer, when the processor enters the C3 state. It is possible for the system to implement a hardware fix to C1e mode on some processor revisions and some packages. This is indicated by OSVW[1] and no workaround is necessary when
OSVW_Length >= 2 and OSVW[1] is zero. An operating system workaround for C3 mode is always necessary, regardless of the setting of OSVW[1].
Fix Planned
C1e state: Yes
C3 state: No

In breve: problemi con le interrupt in risparmio energetico se si usa solo il timer APIC per le interruzioni. Il workaround risolve il problema.

407 Corretto solo nel D (PRESENTE NEL C3)
System May Hang Due to Stalled Probe Data Transfer
Description
Under highly detailed and specific internal timing conditions, a processor that has one or more processor cores in a cache-flushed state following a C1e exit, and one or more cores executing in C0 state, may not complete a data transfer for a probe.
Potential Effect on System
System hang.
Suggested Workaround
Contact your AMD representative for information on a BIOS update. This workaround requires that Clock Power/Timing Control 2 Register[CacheFlushOnHaltTmr] (F3xDC[25:19]) is greater than 01h, which is true under normal circumstances.
Fix Planned
Yes

In breve: in alcune circostanza in cui i core sono in risparmio energetico con la cache disabilitata (C1e), il processore si può bloccare nel probing di quei core. Solo se un registro è impostato in una data maniera, che in circostanze normali non è così...





In definitiva: lo step C3 corregge alcuni bugs. Lo step D ne corregge ancora altri, anche se ne introduce nuovi dovuti alle nuove funzionalità introdotte: probe filter/HT assist (solo in configurazioni server 4p e 8p) e HT link più veloce del NB clock...

Lo step D a mio avviso è meglio del C3... Chissà quando lo vedremo...

Sei un grande. Quando troverai un pò di tempo leggeresti alcuni link su possibili patent di buldozer? Solo tu sei in grado di capire tutte quelle patenti con schemini astrusi.

[OEidolon]

ragazzi propongo la creazione di vie/piazze intestate a bjt2

oppure in alternativa anche un monumento

[Heaven-lord]

salve a tutti:

dovendo scegliere tra:
1)AMD Phenom II X4 940 Black Edition 3,0Ghz 125W Box---->144 euro
2)AMD Phenom II X4 945 4x512KB (3.0 GHz) 95W Deneb Box--->135 euro

quale mi consigliate? considerando anche che un po' di overclock non lo disdegnerò...

[bjt2]

Originariamente inviato da Pihippo

Sei un grande. Quando troverai un pò di tempo leggeresti alcuni link su possibili patent di buldozer? Solo tu sei in grado di capire tutte quelle patenti con schemini astrusi.

Mi pare di aver scritto qualcosa su quei link e il capitano li ha riportati da qualche parte (mi pare in prima pagina)...

Forse sarebbe l'ora di creare un thread dedicato "Aspettando Bulldozer"...

[Pihippo]

Originariamente inviato da bjt2

Mi pare di aver scritto qualcosa su quei link e il capitano li ha riportati da qualche parte (mi pare in prima pagina)...

Forse sarebbe l'ora di creare un thread dedicato "Aspettando Bulldozer"...

In effetti, sarebbè molto bello, materiale verosimile c'è n'è, io mi ero messo a leggere varie patenti postate da un altro utente ed avevo fatto mini sunto, ma sinceramente ci sono delle parti in cui è necessaria proprio competenza tecnica e dove io mi perdo nell'oscurità più assoluta. Secondo me potresti provare magari ad approfondirli un pò tu, sempre se hai tempo e voglia.

[mtk]

Originariamente inviato da MonsterMash

Il problema non è il consumo, ma il calore (e conseguente rumore) e le dimensioni! Come fai a far stare un processore OC + 8800gt in un case grosso quanto un videoregistratore? E poi il rumore delle ventole non ti disturba mentre guardi un film?
Io ho usato un x2 5000+ black edition molto downvoltato su una mobo msi k9a26m (con 780g e uscita hdmi), e ho rallentato tutte le ventole (compresa quella dell'alimentatore micro-atx, altrimenti il rumore mi dava fastidio...

il case per ora e' un thermaltake bach.....ma ho dovuto aprire una botola sulla parte superiore del case in corrispondenza del dissipatore ac freezer extreme......sforava in altezza di 3/4 millimetri
sto guardando i lian li a cubo e i semi slim con mobo ruotata per sostituirlo....
per il rumore della vga uso dei profili attivabili per il game,altrimenti la tengo con ventola al minimo,l unico ronzio e' dovuto alle due ventole aggiunte per il cestello hard disk e per l aria fresca alla vga,ma sono ventole di recupero...quando decidero' il nuovo case credo che aggiungero un kit a liquido per risolvere il problema del rumore
in ogni caso il rumore non mi da' fastidio,anzi il ronzio di sottofondo che spunta al termine di un film o quando il pc e' in standby mi concilia il sonno.....