Prove di OC su asus

[Sterlok]

Salve,

Il principio è che non arrivano watt alla cpu, in esame una i97980XE, su Rampage VI Extreame della ASUS, sto facendo un OC inc ore by usage, ma sono normali i watt che arrvano al processore, devo modficare anche altri valori?? Incollo i settings attuali del mio Bios:

E uno screen di Cor Temp:



Mi e stato spiegato di aumentare piano piano il moltiplicatore, ma vorrei prima capire meglio come aumentare la potenza della CPU e se e il caso di aumentare, grazie

[2024/08/26 16:10:22]
Ai Overclock Tuner [XMP]
XMP [XMP DDR4-3200 15-15-15-35-1.350V]
CPU Strap [100]
BCLK Frequency [100.0000]
ASUS MultiCore Enhancement [Auto]
AVX Instruction Core Ratio Negative Offset [Auto]
AVX-512 Instruction Core Ratio Negative Offset [Auto]
CPU Core Ratio [By Core Usage]
Turbo Ratio Limit 0 [Auto]
Turbo Ratio Cores 0 [Auto]
Turbo Ratio Limit 1 [Auto]
Turbo Ratio Cores 1 [Auto]
Turbo Ratio Limit 2 [Auto]
Turbo Ratio Cores 2 [Auto]
Turbo Ratio Limit 3 [Auto]
Turbo Ratio Cores 3 [Auto]
Turbo Ratio Limit 4 [Auto]
Turbo Ratio Cores 4 [Auto]
Turbo Ratio Limit 5 [Auto]
Turbo Ratio Cores 5 [Auto]
Turbo Ratio Limit 6 [Auto]
Turbo Ratio Cores 6 [Auto]
Turbo Ratio Limit 7 [Auto]
Turbo Ratio Cores 7 [Auto]
Min. CPU Cache Ratio [Auto]
Max. CPU Cache Ratio [Auto]
BCLK Frequency : DRAM Frequency Ratio [Auto]
DRAM Frequency [DDR4-3200MHz]
Xtreme Tweaking [Enabled]
TPU [Keep Current Settings]
CPU SVID Support [Auto]
DRAM CAS# Latency [15]
DRAM RAS# to CAS# Delay [15]
DRAM RAS# PRE Time [15]
DRAM RAS# ACT Time [35]
DRAM Command Rate [Auto]
DRAM RAS# to RAS# Delay [Auto]
DRAM RAS# to RAS# Delay L [Auto]
DRAM REF Cycle Time [Auto]
DRAM Refresh Interval [Auto]
DRAM WRITE Recovery Time [Auto]
DRAM READ to PRE Time [Auto]
DRAM FOUR ACT WIN Time [Auto]
DRAM WRITE to READ Delay [Auto]
DRAM WRITE to READ Delay L [Auto]
DRAM CKE Minimum Pulse Width [Auto]
DRAM Write Latency [Auto]
ODT RTTWR(CHA D0) [Auto]
ODT RTTWR(CHA D1) [Auto]
ODT RTTWR(CHB D0) [Auto]
ODT RTTWR(CHB D1) [Auto]
ODT RTTWR(CHC D0) [Auto]
ODT RTTWR(CHC D1) [Auto]
ODT RTTWR(CHD D0) [Auto]
ODT RTTWR(CHD D1) [Auto]
ODT RTTNOM(CHA D0) [Auto]
ODT RTTNOM(CHA D1) [Auto]
ODT RTTNOM(CHB D0) [Auto]
ODT RTTNOM(CHB D1) [Auto]
ODT RTTNOM(CHC D0) [Auto]
ODT RTTNOM(CHC D1) [Auto]
ODT RTTNOM(CHD D0) [Auto]
ODT RTTNOM(CHD D1) [Auto]
ODT RTTPARK(CHA D0) [Auto]
ODT RTTPARK(CHA D1) [Auto]
ODT RTTPARK(CHB D0) [Auto]
ODT RTTPARK(CHB D1) [Auto]
ODT RTTPARK(CHC D0) [Auto]
ODT RTTPARK(CHC D1) [Auto]
ODT RTTPARK(CHD D0) [Auto]
ODT RTTPARK(CHD D1) [Auto]
Data Rising Slope (CHAB) [Auto]
Data Rising Slope (CHCD) [Auto]
Data Rising Slope Offset (CHAB) [Auto]
Data Rising Slope Offset (CHCD) [Auto]
Cmd Rising Slope (CHAB) [Auto]
Cmd Rising Slope (CHCD) [Auto]
Cmd Rising Slope Offset (CHAB) [Auto]
Cmd Rising Slope Offset (CHCD) [Auto]
Ctl Rising Slope (CHAB) [Auto]
Ctl Rising Slope (CHCD) [Auto]
Ctl Rising Slope Offset (CHAB) [Auto]
Ctl Rising Slope Offset (CHCD) [Auto]
Data Falling Slope (CHAB) [Auto]
Data Falling Slope (CHCD) [Auto]
Data Falling Slope Offset (CHAB) [Auto]
Data Falling Slope Offset (CHCD) [Auto]
Cmd Falling Slope Falling Slope (CHAB) [Auto]
Cmd Falling Slope Falling Slope (CHCD) [Auto]
Cmd Falling Slope Offset (CHAB) [Auto]
Cmd Falling Slope Offset (CHCD) [Auto]
Ctl Falling Slope (CHAB) [Auto]
Ctl Falling Slope (CHCD) [Auto]
Ctl Falling Slope Offset (CHAB) [Auto]
Ctl Falling Slope Offset (CHCD) [Auto]
IMC Interleaving [Auto]
Channel Interleaving [Auto]
Rank Interleaving [Auto]
MC Vref(CHA) [Auto]
MC Vref(CHB) [Auto]
MC Vref(CHC) [Auto]
MC Vref(CHD) [Auto]
DRAM Vref(CHA) [Auto]
DRAM Vref(CHA) [Auto]
DRAM Vref(CHC) [Auto]
DRAM Vref(CHC) [Auto]
CTL Vref (CHA) [Auto]
CTL Verf (CHB) [Auto]
CTL Vref (CHC) [Auto]
CTL Verf (CHD) [Auto]