Discussione seria sulle pipeline!

[Betha23]

Prima di dirvi la mia teoria rispondete a questa mia domanda, per eseguire uno stadio delle pipeline ci vuole un ciclo di clock vero?

[ev8]

Originariamente inviato da Betha23
[b]Prima di dirvi la mia teoria rispondete a questa mia domanda, per eseguire uno stadio delle pipeline ci vuole un ciclo di clock vero?

Si.

[ev8]

Ci vuole uno ed un solo ciclo, altrimenti non sarebbe uno "stadio di una pipeline".

[Betha23]

Ok quindi per eseguire un calcolo nella pipeline dell'Athlon ci vogliono 10 cicli (10 stadi della pipeline) e nel P4 20 cicli (20 stadi delle pipeline) vero?

[Athlon]

Ad ogni ciclo di clock ogni stadio mette nel registro di Pipe il risultato delle sue operazioni ... al clock successivo lo stadio seguente accede alo stesso registro per avre i dati in Input

[ev8]

Originariamente inviato da Betha23
[b]Ok quindi per eseguire un calcolo nella pipeline dell'Athlon ci vogliono 10 cicli (10 stadi della pipeline) e nel P4 20 cicli (20 stadi delle pipeline) vero?

Dipende dal tipo di istruzione e dagli operandi utilizzati. Il tuo esempio cmq è corretto nel caso di un'operazione su numeri interi con operandi nei registri.

[ev8]

E, nel caso del pentium4, che l'istruzione sia già stata precodificata.

[Betha23]

Allora supponendo che ci vogliono 20 cicli di clock per eseguire un operazione sugli interi su di un P4.......su un Athlon ce ne vorrebbero 10!

E quindi un operazione che entra nella pipeline di un P4 ci mette 20 cicli per essere eseguita......e nel Athlon 10! Quindi sempre in teoria ci vorrebbe un P4 di doppia frequenza per stare dietro all'Athlon!

Mi confermate quello che sto dicendo?

Altra cosa.........io sto parlando di ALU.......ma quanti stadi delle pipeline ha l'FPU del Athlon?? e Del p4??

[ev8]

Originariamente inviato da Betha23
[b]Allora supponendo che ci vogliono 20 cicli di clock per eseguire un operazione sugli interi su di un P4.......su un Athlon ce ne vorrebbero 10!

E quindi un operazione che entra nella pipeline di un P4 ci mette 20 cicli per essere eseguita......e nel Athlon 10! Quindi sempre in teoria ci vorrebbe un P4 di doppia frequenza per stare dietro all'Athlon!

Mi confermate quello che sto dicendo?

Quello a cui ti riferisci tu non è il numero di istruzioni nell'unità di tempo, ma bensì al tempo che impiega una singola istruzione per essere completata(latenza).Con 20 stadi, in ogni ciclo vengono attraversati 20stadi della pipeline e non 10 come nel caso del K7 => il p4 impiega 20 cicli per eseguire 20 istruzioni, il K7 impiega 10cicli per eseguire 10 istruzioni. Fatti i conti, la lunghezza della pipline non ha effetto sul numero di istruzioni eseguite nell'unità di tempo.

Altra cosa.........io sto parlando di ALU.......ma quanti stadi delle pipeline ha l'FPU del Athlon?? e Del p4?? [/quote]
P4 e K7 non hanno più di una pipeline per il calcolo in FP, e di lughezza diversa.
Per fare un'esempio, una somma il p4 impiega 4 cicli in più di una normale operazione intera, nel caso del K7 i cicli aggiuntivi sono 3.

[ev8]

Originariamente inviato da Betha23
[b]Allora supponendo che ci vogliono 20 cicli di clock per eseguire un operazione sugli interi su di un P4.......su un Athlon ce ne vorrebbero 10!

E quindi un operazione che entra nella pipeline di un P4 ci mette 20 cicli per essere eseguita......e nel Athlon 10! Quindi sempre in teoria ci vorrebbe un P4 di doppia frequenza per stare dietro all'Athlon!

Mi confermate quello che sto dicendo?

Quello a cui ti riferisci tu non è il numero di istruzioni nell'unità di tempo, ma bensì al tempo che impiega una singola istruzione per essere completata(latenza).Con 20 stadi, in ogni ciclo vengono attraversati 20stadi della pipeline e non 10 come nel caso del K7 => il p4 impiega 20 cicli per eseguire 20 istruzioni, il K7 impiega 10cicli per eseguire 10 istruzioni. Fatti i conti, la lunghezza della pipline non ha effetto sul numero di istruzioni eseguite nell'unità di tempo.

[b]

Altra cosa.........io sto parlando di ALU.......ma quanti stadi delle pipeline ha l'FPU del Athlon?? e Del p4??

P4 e K7 non hanno più di una pipeline per il calcolo in FP, e di lughezza diversa.
Per fare un'esempio, una somma il p4 impiega 4 cicli in più di una normale operazione intera, nel caso del K7 i cicli aggiuntivi sono 3.
Ecco, questo era il post corretto

[ev8]

P4 e K7 HANNO più di una pipeline ...
Oggi ho fumato troppo

[Betha23]

Originariamente inviato da ev8
[b]P4 e K7 HANNO più di una pipeline ...
Oggi ho fumato troppo

Brutta bestia la maria!

Cmq non ti ho ben capito..........facendo conto che io devo eseguire una sola operazione.........nel P4 avendo 20 stadi mi ci vorrebbero si o no 20 cicli?? e nel althlon ce ne vorrebbero 10?

Io intendo semplicemente eseguendo un operazione non cose più complicate o parallelismi.

[Freeze]

Scusate ma...cos'è una pipeline?

[Betha23]

Originariamente inviato da Freeze
[b]Scusate ma...cos'è una pipeline?

La pipeline è la vera e proprio catena di montaggio dove viene eseguita un istruzione.

[ev8]

Originariamente inviato da Betha23
[b]

Brutta bestia la maria!

Cmq non ti ho ben capito..........facendo conto che io devo eseguire una sola operazione.........nel P4 avendo 20 stadi mi ci vorrebbero si o no 20 cicli?? e nel althlon ce ne vorrebbero 10?

Io intendo semplicemente eseguendo un operazione non cose più complicate o parallelismi.

La tua affermazione in teoria sarebbe esatta, ma non accade QUASI mai che la cpu debba eseguire una singola operazione e poi fermarsi per attenderne il risultato.La struttura a pipeline è stata introdotta proprio per questo, perchè in genere le istruzioni in un programma non dipendono l'una dalle altre, e quindi possono riempire tutta la pipeline, una per ogni stadio.
Quel QUASI è la causa del fatto che una cpu come il P4 sia più lenta, a parità di frquenza, rispetto ad un K7.

[Betha23]

Originariamente inviato da ev8
[b]
La tua affermazione in teoria sarebbe esatta, ma non accade QUASI mai che la cpu debba eseguire una singola operazione e poi fermarsi per attenderne il risultato.La struttura a pipeline è stata introdotta proprio per questo, perchè in genere le istruzioni in un programma non dipendono l'una dalle altre, e quindi possono riempire tutta la pipeline, una per ogni stadio.
Quel QUASI è la causa del fatto che una cpu come il P4 sia più lenta, a parità di frquenza, rispetto ad un K7.

si si questo lo so bene! Volevo capire se ero riuscito a capire (che gioco di parole) questo benedetto "svuotamento" e "riempmento" delle pipeline!

Grazie ................l'interessante sarà vedere quale delle 2 soluzioni pagherà di più, quella della velocità del P4 oconservativa dell'Athlon.

[alexmaz]

Per evitare confusione sottolineo il fatto che ogni ciclo del P4 è ovviamente più breve di quello di un K7... e qui sta il senso della pipeline così profonda: la frequenza sale molto e se si verificano le condizioni ottimali (molte istruzioni da eseguire, poche dipendenze, pochi salti ) la cpu va molto forte. Di fatto queste condizioni ottimali si verificano raramente ed è in parte per questo che Intel ha pensato all'HyperThreading...

[Betha23]

Originariamente inviato da alexmaz
[b]Per evitare confusione sottolineo il fatto che ogni ciclo del P4 è ovviamente più breve di quello di un K7... e qui sta il senso della pipeline così profonda: la frequenza sale molto e se si verificano le condizioni ottimali (molte istruzioni da eseguire, poche dipendenze, pochi salti ) la cpu va molto forte. Di fatto queste condizioni ottimali si verificano raramente ed è in parte per questo che Intel ha pensato all'HyperThreading...

Ed ecco spiegato il motivo per cui il P4 ha frequenze maggiori con prestazioni minori (a pari frequenza).

Sinceramente non trovo il motivo per cui la criticate tanto?

[riaw]

Originariamente inviato da Betha23
[b]

Sinceramente non trovo il motivo per cui la criticate tanto?

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[ev8]

Originariamente inviato da alexmaz
[b]Per evitare confusione sottolineo il fatto che ogni ciclo del P4 è ovviamente più breve di quello di un K7... e qui sta il senso della pipeline così profonda: la frequenza sale molto e se si verificano le condizioni ottimali (molte istruzioni da eseguire, poche dipendenze, pochi salti ) la cpu va molto forte. Di fatto queste condizioni ottimali si verificano raramente ed è in parte per questo che Intel ha pensato all'HyperThreading...

L'HT ha senso sul pentium4 perchè la pipeline è troppo lunga ed incasinata(per gli ingegneri intel ) , tanto da rendere inapplicabili i controlli inter-stage (tipo MIPS o EV6).Sdoppiare i registri e montare all'esterno della pipeline il controllo per due thread è sicuramente più facile, ma non è cmq un gran passo in avanti dal punto di vista tecnico( tutti possono farlo ).
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