View Full Version : Discussione seria sulle pipeline!
Prima di dirvi la mia teoria rispondete a questa mia domanda, per eseguire uno stadio delle pipeline ci vuole un ciclo di clock vero? :confused:
Originariamente inviato da Betha23
[B]Prima di dirvi la mia teoria rispondete a questa mia domanda, per eseguire uno stadio delle pipeline ci vuole un ciclo di clock vero? :confused:
Si.
Ci vuole uno ed un solo ciclo, altrimenti non sarebbe uno "stadio di una pipeline".
Ok quindi per eseguire un calcolo nella pipeline dell'Athlon ci vogliono 10 cicli (10 stadi della pipeline) e nel P4 20 cicli (20 stadi delle pipeline) vero?
Ad ogni ciclo di clock ogni stadio mette nel registro di Pipe il risultato delle sue operazioni ... al clock successivo lo stadio seguente accede alo stesso registro per avre i dati in Input
Originariamente inviato da Betha23
[B]Ok quindi per eseguire un calcolo nella pipeline dell'Athlon ci vogliono 10 cicli (10 stadi della pipeline) e nel P4 20 cicli (20 stadi delle pipeline) vero?
Dipende dal tipo di istruzione e dagli operandi utilizzati. Il tuo esempio cmq è corretto nel caso di un'operazione su numeri interi con operandi nei registri.
E, nel caso del pentium4, che l'istruzione sia già stata precodificata.
Allora supponendo che ci vogliono 20 cicli di clock per eseguire un operazione sugli interi su di un P4.......su un Athlon ce ne vorrebbero 10!
E quindi un operazione che entra nella pipeline di un P4 ci mette 20 cicli per essere eseguita......e nel Athlon 10! Quindi sempre in teoria ci vorrebbe un P4 di doppia frequenza per stare dietro all'Athlon! :rolleyes:
Mi confermate quello che sto dicendo?
Altra cosa.........io sto parlando di ALU.......ma quanti stadi delle pipeline ha l'FPU del Athlon?? e Del p4?? :confused:
Originariamente inviato da Betha23
[B]Allora supponendo che ci vogliono 20 cicli di clock per eseguire un operazione sugli interi su di un P4.......su un Athlon ce ne vorrebbero 10!
E quindi un operazione che entra nella pipeline di un P4 ci mette 20 cicli per essere eseguita......e nel Athlon 10! Quindi sempre in teoria ci vorrebbe un P4 di doppia frequenza per stare dietro all'Athlon! :rolleyes:
Mi confermate quello che sto dicendo?
Quello a cui ti riferisci tu non è il numero di istruzioni nell'unità di tempo, ma bensì al tempo che impiega una singola istruzione per essere completata(latenza).Con 20 stadi, in ogni ciclo vengono attraversati 20stadi della pipeline e non 10 come nel caso del K7 => il p4 impiega 20 cicli per eseguire 20 istruzioni, il K7 impiega 10cicli per eseguire 10 istruzioni. Fatti i conti, la lunghezza della pipline non ha effetto sul numero di istruzioni eseguite nell'unità di tempo.
Altra cosa.........io sto parlando di ALU.......ma quanti stadi delle pipeline ha l'FPU del Athlon?? e Del p4?? :confused: [/quote]
P4 e K7 non hanno più di una pipeline per il calcolo in FP, e di lughezza diversa.
Per fare un'esempio, una somma il p4 impiega 4 cicli in più di una normale operazione intera, nel caso del K7 i cicli aggiuntivi sono 3.
Originariamente inviato da Betha23
[B]Allora supponendo che ci vogliono 20 cicli di clock per eseguire un operazione sugli interi su di un P4.......su un Athlon ce ne vorrebbero 10!
E quindi un operazione che entra nella pipeline di un P4 ci mette 20 cicli per essere eseguita......e nel Athlon 10! Quindi sempre in teoria ci vorrebbe un P4 di doppia frequenza per stare dietro all'Athlon! :rolleyes:
Mi confermate quello che sto dicendo?
Quello a cui ti riferisci tu non è il numero di istruzioni nell'unità di tempo, ma bensì al tempo che impiega una singola istruzione per essere completata(latenza).Con 20 stadi, in ogni ciclo vengono attraversati 20stadi della pipeline e non 10 come nel caso del K7 => il p4 impiega 20 cicli per eseguire 20 istruzioni, il K7 impiega 10cicli per eseguire 10 istruzioni. Fatti i conti, la lunghezza della pipline non ha effetto sul numero di istruzioni eseguite nell'unità di tempo.
[B]Altra cosa.........io sto parlando di ALU.......ma quanti stadi delle pipeline ha l'FPU del Athlon?? e Del p4?? :confused:
P4 e K7 non hanno più di una pipeline per il calcolo in FP, e di lughezza diversa.
Per fare un'esempio, una somma il p4 impiega 4 cicli in più di una normale operazione intera, nel caso del K7 i cicli aggiuntivi sono 3.
Ecco, questo era il post corretto :D
P4 e K7 HANNO più di una pipeline ...
Oggi ho fumato troppo :D:D:D
Originariamente inviato da ev8
[B]P4 e K7 HANNO più di una pipeline ...
Oggi ho fumato troppo :D:D:D
Brutta bestia la maria! :D
Cmq non ti ho ben capito..........facendo conto che io devo eseguire una sola operazione.........nel P4 avendo 20 stadi mi ci vorrebbero si o no 20 cicli?? e nel althlon ce ne vorrebbero 10? :confused:
Io intendo semplicemente eseguendo un operazione non cose più complicate o parallelismi.
Scusate ma...cos'è una pipeline?
Originariamente inviato da Freeze
[B]Scusate ma...cos'è una pipeline?
La pipeline è la vera e proprio catena di montaggio dove viene eseguita un istruzione.
Originariamente inviato da Betha23
[B]
Brutta bestia la maria! :D
Cmq non ti ho ben capito..........facendo conto che io devo eseguire una sola operazione.........nel P4 avendo 20 stadi mi ci vorrebbero si o no 20 cicli?? e nel althlon ce ne vorrebbero 10? :confused:
Io intendo semplicemente eseguendo un operazione non cose più complicate o parallelismi.
La tua affermazione in teoria sarebbe esatta, ma non accade QUASI mai che la cpu debba eseguire una singola operazione e poi fermarsi per attenderne il risultato.La struttura a pipeline è stata introdotta proprio per questo, perchè in genere le istruzioni in un programma non dipendono l'una dalle altre, e quindi possono riempire tutta la pipeline, una per ogni stadio.
Quel QUASI è la causa del fatto che una cpu come il P4 sia più lenta, a parità di frquenza, rispetto ad un K7.
Originariamente inviato da ev8
[B]
La tua affermazione in teoria sarebbe esatta, ma non accade QUASI mai che la cpu debba eseguire una singola operazione e poi fermarsi per attenderne il risultato.La struttura a pipeline è stata introdotta proprio per questo, perchè in genere le istruzioni in un programma non dipendono l'una dalle altre, e quindi possono riempire tutta la pipeline, una per ogni stadio.
Quel QUASI è la causa del fatto che una cpu come il P4 sia più lenta, a parità di frquenza, rispetto ad un K7.
si si questo lo so bene! Volevo capire se ero riuscito a capire (che gioco di parole) questo benedetto "svuotamento" e "riempmento" delle pipeline! ;)
Grazie ................l'interessante sarà vedere quale delle 2 soluzioni pagherà di più, quella della velocità del P4 oconservativa dell'Athlon. ;)
Per evitare confusione sottolineo il fatto che ogni ciclo del P4 è ovviamente più breve di quello di un K7... e qui sta il senso della pipeline così profonda: la frequenza sale molto e se si verificano le condizioni ottimali (molte istruzioni da eseguire, poche dipendenze, pochi salti :D ) la cpu va molto forte. Di fatto queste condizioni ottimali si verificano raramente ed è in parte per questo che Intel ha pensato all'HyperThreading...
Originariamente inviato da alexmaz
[B]Per evitare confusione sottolineo il fatto che ogni ciclo del P4 è ovviamente più breve di quello di un K7... e qui sta il senso della pipeline così profonda: la frequenza sale molto e se si verificano le condizioni ottimali (molte istruzioni da eseguire, poche dipendenze, pochi salti :D ) la cpu va molto forte. Di fatto queste condizioni ottimali si verificano raramente ed è in parte per questo che Intel ha pensato all'HyperThreading...
Ed ecco spiegato il motivo per cui il P4 ha frequenze maggiori con prestazioni minori (a pari frequenza).
Sinceramente non trovo il motivo per cui la criticate tanto? :confused:
Originariamente inviato da Betha23
[B]
Sinceramente non trovo il motivo per cui la criticate tanto? :confused:
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Originariamente inviato da alexmaz
[B]Per evitare confusione sottolineo il fatto che ogni ciclo del P4 è ovviamente più breve di quello di un K7... e qui sta il senso della pipeline così profonda: la frequenza sale molto e se si verificano le condizioni ottimali (molte istruzioni da eseguire, poche dipendenze, pochi salti :D ) la cpu va molto forte. Di fatto queste condizioni ottimali si verificano raramente ed è in parte per questo che Intel ha pensato all'HyperThreading...
L'HT ha senso sul pentium4 perchè la pipeline è troppo lunga ed incasinata(per gli ingegneri intel :D ) , tanto da rendere inapplicabili i controlli inter-stage (tipo MIPS o EV6).Sdoppiare i registri e montare all'esterno della pipeline il controllo per due thread è sicuramente più facile, ma non è cmq un gran passo in avanti dal punto di vista tecnico( tutti possono farlo :D ).
Ciauzz alex
Originariamente inviato da Betha23
[b]
Ed ecco spiegato il motivo per cui il P4 ha frequenze maggiori con prestazioni minori (a pari frequenza).
Sinceramente non trovo il motivo per cui la criticate tanto? :confused:
Io non critico tanto :mad: :D
Cmq, come accennava riaw, tieni conto che nello spazio occupato da un P4 ci stanno 2 core K7 in SMT :)
Come disse il saggio: i pentium 4 li vogliamo vedere solo nei server!!! :D
Originariamente inviato da ev8
Io non critico tanto :mad: :D
Cmq, come accennava riaw, tieni conto che nello spazio occupato da un P4 ci stanno [b]2 core K7 in SMT :)
Come disse il saggio: i pentium 4 li vogliamo vedere solo nei server!!! :D
Si in effetti non capisco perchè il core del P4 sia cosi grande?? :confused:
Originariamente inviato da Betha23
[B]
Si in effetti non capisco perchè il core del P4 sia cosi grande?? :confused:
Perchè la pipeline è spropositatamente lunga,è fatta male ed ha bisogno di circuiti aggiuntivi per il predecode(anche se su quest'ultimo punto sono daccordo con intel perchè permette di consumare meno W :) ).
ev8 ma tu da dove trai informazioni così approfondite sui vari processori? :)
Originariamente inviato da alexmaz
[B]ev8 ma tu da dove trai informazioni così approfondite sui vari processori? :)
;)
Cmq le basi le puoi trovare anche nelle presentazioni o nei papers o nei patent dei produttori.
Es. quest'ultimo ISSCC è molto interessante:
ftp://download.intel.com/pressroom/temp/isscc.pdf
riaw potresti spiegarti meglio che non ho capito??:D
ciao ciao
p.s. Concorco pienamente per i €(lol)
Originariamente inviato da Betha23
[B]
La pipeline è la vera e proprio catena di montaggio dove viene eseguita un istruzione.
Potresti spiegarti meglio? :)
Cmq...grazie riaw...nonstante la lunghezza del tuo post sei stato davvero di grande utilità :rolleyes:
la prossima volta puoi scrivere meno sinteticamente? :rolleyes: :mad:
sono 2 strategie diverse, ma che in sostanza si equvalgono
tipico esempio automobilistico.
il p4 è una formula uno che per compiere un tragitto si deve fermare più volte a far benzina(svuotamento pipe)
l'athlon è un porsce, che pura andando più lentamente compie lo stesso tragitto nello stesso tempo poichè non deve fermarsi.
con il salire in velocità però la f1 consuma tanta benza uguale, e quindi si ferma lo stesso numero di volte, ma il tempo diminuisce.
questo per dire che più sale in frequenza più il p4 è efficente.
bisogna vedere a che frq si raggiunge una buona efficenza.
dal 1500 al 2000 è migliorato molto , ma non abbastanza
Originariamente inviato da checo
[B]sono 2 strategie diverse, ma che in sostanza si equvalgono
tipico esempio automobilistico.
il p4 è una formula uno che per compiere un tragitto si deve fermare più volte a far benzina(svuotamento pipe)
l'athlon è un porsce, che pura andando più lentamente compie lo stesso tragitto nello stesso tempo poichè non deve fermarsi.
con il salire in velocità però la f1 consuma tanta benza uguale, e quindi si ferma lo stesso numero di volte, ma il tempo diminuisce.
questo per dire che più sale in frequenza più il p4 è efficente.
Non ho capito il tuo ragionamento...
Cmq se il p4 scala meglio del K7 è perchè ha un FSB superiore, e quindi, con l'aumentare della frequenza, tende ad utilizzarlo meglio.
[B]bisogna vedere a che frq si raggiunge una buona efficenza.
dal 1500 al 2000 è migliorato molto , ma non abbastanza
Originariamente inviato da ev8
[B]
Non ho capito il tuo ragionamento...
Cmq se il p4 scala meglio del K7 è perchè ha un FSB superiore, e quindi, con l'aumentare della frequenza, tende ad utilizzarlo meglio.
[B]
mi pareva semplice il ragionamento.
il p4, va più veolce, ma si ferma spesso e svuotare la pipe.
il k7 va meno veloce, ma si ferma mooolto meno.
Originariamente inviato da checo
[B]
mi pareva semplice il ragionamento.
il p4, va più veolce, ma si ferma spesso e svuotare la pipe.
il k7 va meno veloce, ma si ferma mooolto meno.
Ops :D avevo confuso con un'altra roba...
Cmq, se vogliamo essere pignoli, il p4 si ferma meno spesso del K7, è solo che per fare il pieno ci mette il doppio del tempo! :D:D
Originariamente inviato da ev8
[B]
Ops :D avevo confuso con un'altra roba...
Cmq, se vogliamo essere pignoli, il p4 si ferma meno spesso del K7, è solo che per fare il pieno ci mette il doppio del tempo! :D:D
vabbè oltre a fare benzina si beve anche na birretta.:D
poi si potrebbe dire che se tira troppo si scalda e deve andare a 100kmh per un po.
solo che è difficilissimo che succeda.
Tedturb0
01-02-2002, 19:52
ma da quanto mi risulta le pipline non sono una o due , bensì 4 o 6 (non mi ricordo)
e gli stadi se non sbaglio erano 22
io mipare di aver letto che il massimo di prestazioni si ottiene con 8-10 stadi.
quindi o Intel ha creato dei compilatori Straultraottimizzati, oppure per gestire codice per un chip a 20+ stadi e superscalare a 4-6 pipeline ha integrato la palla di vetro dentro il chip :)
volevo chiedere: ero rimasto ai MIPS che erano i CHIP piu performanti (insieme ai DEC Alpha etc etc)
ma l'R10000 a 400 (mi pare) mhz viene considerato ormai roba da museo
Attualmente MIPS che chip produce? e dove vengono montati?
Originariamente inviato da Tedturb0
[B]ma da quanto mi risulta le pipline non sono una o due , bensì 4 o 6 (non mi ricordo)
Teoricamente, il maggior numero di pipeline parallele si ottiene nella fase di esecuzione. più precisamente:Memory Store,Memory Load,ALU 1 Double speed,Integer Operation Normal speed,FP Execute,FP Move,ALU 0 Double speed, quindi sono 7.
e gli stadi se non sbaglio erano 22
Quello è molto variabile.
io mipare di aver letto che il massimo di prestazioni si ottiene con 8-10 stadi.
Si ma è molto indicativo.
[i]quindi o Intel ha creato dei compilatori Straultraottimizzati, oppure per gestire codice per un chip a 20+ stadi e superscalare a 4-6 pipeline ha integrato la palla di vetro dentro il chip :)
volevo chiedere: ero rimasto ai MIPS che erano i CHIP piu performanti (insieme ai DEC Alpha etc etc)
ma l'R10000 a 400 (mi pare) mhz viene considerato ormai roba da museo
Attualmente MIPS che chip produce? e dove vengono montati?
Adesso non ho tempo per quest'ultima domanda! stò uscendo!!!!!!! :D :D :D
Jashugan
02-02-2002, 09:58
Per chi chiedeva cos'era una (o un) pipeline: è un metodo che consiste nel suddividere una istruzione in tante parti quante sono gli stadi. In questa maniera ogni parte del processore può eseguire in parallelo alcune operazioni, riducendo di molto il tempo di esecuzione. Non so se il disegno che mostrerò sarà chiaro, ma lo spero:
a b c d
1
2 1
3 2 1
4 3 2 1
5 4 3 2
6 5 4 3
a,b,c,d sono gli stadi, i numeri indicano l'istruzione in ordine temporale crescente.
Stando a vedere il disegno, parrebbe che aumentando il pipeline si migliora l'efficienza. Questo è vero a meno di Data Hazard o di Data Miss.
Mi spiego meglio: supponiamo che le 4 fasi a,b,c,d rappresentino fetching, decoding, executing e storing.
Supponiamo che l'istruzione 2 abbia bisoogno di dati in memoria per effettuare i suoi conti: ecco allora che siamo in questa situazione:
a b c d
1
2 1
3 2 1
1
4 3 2
E si perde uno stadio, oltre a causare un buco nella pipeline (il mio disegno non è chiaro purtroppo).
Peggio si ha quando avviene il Data miss: in caso di branching (se... allora vai a....), il processore deve fare una scelta: avviene il caso A oppure non avviene? Se indovina la pipeline è perfetta. Ma se non indovina, la pipeline deve essere svuotata! Ed è qua il grossissimo pericolo delle pipe lunghe.
Per quanto riguarda K7: pipeline ALu a 10 stadi e FPU a 15. Ora vado, devo fare un dolce!!!!!
Originariamente inviato da Tedturb0
[B]...
volevo chiedere: ero rimasto ai MIPS che erano i CHIP piu performanti (insieme ai DEC Alpha etc etc)
ma l'R10000 a 400 (mi pare) mhz viene considerato ormai roba da museo
Attualmente MIPS che chip produce? e dove vengono montati?
Il mips più veloce che c'è in giro adesso è l'R14000 che và a 500MHz( :( ), ma nella sostanza è simile all'R10000 da te indicato.
Non è un gran chè veloce, ma, come dico spesso, la potenza di calcolo non è tutto. I server della SGI utilizzano sistemi di intercomunicazione tra le cpu di primordine e questo li rende molto scalabili (dagli 8-16p in sù).
Il mips ha altri vantaggi che lo rendono comodo da integrare in più ampi sistemi di calcolo(es. le latenze basse,i comandi facili da usare, ecc..), un esempio su tutti è l'EE (PS2)... questo non è cmq l'argomento della disciscussione...
Se vuoi farti un'idea delle prestazioni, c'è il DB della spec
http://www.spec.org/osg/cpu2000/results/
oppure quello semplificato di Ace, che però è stato ignorato in una mia discussione precedente :mad: , quindi non ve lo metto :p :D
Tedturb0
02-02-2002, 12:22
ma leggevo mi pare almeno sul sito della mips che c'erano degli UltraMIPS o qualcosa di simile:
forse in quei modelli è cambiata la strategia di progettazione?
Tedturb0
02-02-2002, 12:31
no adesso fanno MIPS32 e MIPS64 e li classificano con i k...
non so cosa sia, ma credo che siano un bel po avanti rispetto agli R2/3000 based
Originariamente inviato da Tedturb0
[B]ma leggevo mi pare almeno sul sito della mips che c'erano degli UltraMIPS o qualcosa di simile:
forse in quei modelli è cambiata la strategia di progettazione?
Francamente non ricordo i nomi ufficiali dei progetti,da quello che ho visto io cmq si parla si on chip SMP.
Tieni presente che cmq tutti i produttori hanno dei progetti,a breve e/o a lungo termine e questi possono essere più o meno pubblicizzati.
Originariamente inviato da Tedturb0
[B]no adesso fanno MIPS32 e MIPS64 e li classificano con i k...
non so cosa sia, ma credo che siano un bel po avanti rispetto agli R2/3000 based
In che senso MIPS32/MIPS64 ?
k sta per kilo?
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