Primi chip Flash NAND da STM
STMicroelectronics ha avviato la produzione in volumi di chip NAND-Flash da 1Gbit e 512Mbit, ovvero i primi prodotti NAND-Flash della compagnia. Secondo quanto riportato nella press-release rilasciata dalla compagnia NAND1G e NAND512 saranno disponibili in due versioni, una a 1,8V e una a 3,0V (rispettivamente NAND01GR3A, NAND512R3A e NAND01GW3A, NAND512W3A).
La domanda per questo tipo di memorie dovrebbe salire in modo considerevole durante il 2004 poiché questo tipo di memorie è particolarmente indicato per dispositivi consumer quali player MP3, sistemi palmari e cellulari 3G. I nuovi chip sono in grado di fornire un elevato throughput dei dati, assieme ad una elevata densità, alta velocità di scrittura e basso consumo energetico.
Di seguito alcune informazioni tecniche tratte dal comunicato stampa:
"The NAND512 and NAND1G memories are organized respectively into a total of 32 pages by 4096 and by 8192 nominal blocks, that can be read and programmed as a whole; the block erase time is just 2ms. The size of the page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The spare bytes are typically used for Error Correction Codes, software flags or Bad-Block identification. A Copy-Back Program mode enables data stored in one page to be programmed directly into another without the need for external buffering, a feature that would typically be used to move the data in the event of failure of a Page Program operation due to a defective block. Each block is specified for 100,000 Program and Erase cycles, and 10-year data retention.
The Address lines and Data Input/Output signals are multiplexed onto an 8-bit bus, reducing the pin count and allowing the use of a modular pin-out which enables system upgrades to higher density devices without changing the footprint. Each device has a Cache Program feature to improve the throughput for large files. This Cache Program loads the data into a cache memory while the previous data is transferred to the page buffer and programmed into the memory array.
Device options include 'Automatic Page 0 Read after Power Up', intended for applications that boot from the NAND memory; and 'Chip Enable Don't Care', which allows the microcontroller to manage NAND operations more efficiently. The 'Chip Enable Don't Care' option also simplifies the use of NAND Flash in combination with other types of memory such as NOR and SRAM - memory combinations are often used where faster devices are needed for code and working memory, but where the much lower cost and higher density NAND memory is preferable for music files or images, for example.
In addition, a unique device identifier can be programmed in-factory, and a User Programmable Serial number supports increased security in the target application. Open source reference software algorithms are available to extend the lifetime of the device, including: Error Correction Code (ECC), to identify and correct errors in the data; Bad Block Management (BBM), to recognize and replace a block that fails in Erase or Program operations by copying its data to a valid block; Garbage Collection, to identify and remove invalid pages in a block and copy valid pages to a free area of another block; and Wear Leveling, to optimize the aging of the device by distributing Erase and Program operations among all the blocks. "