Hardware Upgrade Forum - View Single Post - [Thread Ufficiale] CPU Zen 14/12/7nm: AMD Ryzen!

Angelonero87 · 25-10-2018, 17:55

Stavo guardando questo video e ho trovato questo commento interessante su IF
https://www.youtube.com/watch?v=PHBsR1Y68G8

brad morris

I have worked out the reason why Ryzen has the issues with gaming performance.

It is because the data path for the memory traffic from CCX0 and CCX1 to the system memory, over the Infinity fabric, is effectively the same as a three node LAN with a store and forward switch in the middle (AMD call it a CAKE) connecting the three nodes of the network up. Each connection transfers data at 32bytes/cycle at ram speed making the entire trip from cpu to memory relatively slow at about 1600Mhz. The switch has to work like a traffic cop and merge the traffic from both pipes connected to each CCX into a single 32 byte/cycle pipe that connects to the memory controller, cutting the bandwidth available to each CCX in half.

The dual channel Ram itself is limited to accepting 32 bytes/cycle so there is no benefit increasing the pipe size connecting the memory to the fabric. Generally the memory access network is fine because memory accesses are by nature bursty and not constant so there are gaps and the queue at the switch in the middle smooths things out.

Running cinebench or blender type loads perform well. The available 16 byte/cycle available to each CCX module is enough for the CPU to perform well. If you play a game though, The GPU is connected to the network and needs to access the Memory controller over the same 32 byte/cycle pipe that connects the memory controller to the fabric. Now instead of 16 bytes/cycle available to each CCX, the GPU is also taking say, 30% of the available bandwidth only leaving say 8-12 bytes/cycle available to the threads from eachs CCX. that means the requests have to wait through longe queues at the switch and each thread has to remain idle for a fraction longer waiting for memory access.

Faster memory helps because it provides more cycles per second to shift the backlog a the switch. Because the speed from cpu to memory is speed limited, the memory controller doesnt need to buffer much and ends up with either being fully busy or doing nothing

Intel uses the ring bus that runs at least twice the frequency of the Ram making the trip from cpu to the memory controller buffer fast with reduced latency. Once in the buffer, the controller to memory link is at the same speed as the AD but it is only a short trip. the controller can write the data to memory as soon as there is a write slot available.

Infinity Fabric is a marketing blanket term invented by AMD and actually covers the data transport and the management layer. I am talking about the data transport layer. Make no mistake, it is a network on a Chip. It does not use TCPIP, it has different protocols but the principles of network traffic and network bottlenecks remains the same. Road traffic getting traffic jams at peak hour because two main feeder roads merge into one road with out any extra lanes is exactly the same principle. Increasing ram frequency is the same as giving the merged road a higher speed limit .

The infinity Fabric that you are thinking about in terms of frequency is just the transport mechanism. Memory reads and writes are the work that is done by using the transport mechanism and that work takes time to complete. The time the System Ram takes to complete a memory transaction is determined by the CAS timings and sub timings that together determine the total transaction time cost involved. The Fabric has teh capacity to carry 4 memory transactions at a time. A single ram write request takes 60-100 ns to complete depending on how tight the timings are set. The time to complete the transaction and be ready for the next one is what is being reported as Latency in the aida64 latency tests. If the memory is busy with servicing requests from cpu 0-3, the next load of thread memory access requests from cpu4-7 have to wait until the memory is available to get a turn. Threads waiting for access to memory are sitting idle not processing anything.

CPU cache is clocked to the CPU clock and is effectively fixed. The Ram frequency sets the speed limit on the data transport. More cycles available on the fabric network, gives the CPU more opportunities for the cpu threads to have their turn to utilize the system Ram. tighter timings means the waiting time before the memory can deal with the next send is lower.

AMD and Intel have taken different approaches to accessing memory. The relatively slow Infinity fabric means that the data is speed limited all the way from the CPU to the Memory controller incurring a time cost but the memory controller does not need to buffer anything and processes the requests as they arrive. The time cost is seen as the higher latency scores in the benchmarks. The higher latency does benefit SMT because each thread gets more opportunity to do some work.

Intel's ring bus is about double the speed between cpu to memory controller but it relies on the memory controller buffering the fast arriving data an manageing the data access in the last hop to the ram silicon. that makes more efficient use of the available Ram cycles in the last hop from controller to as the Ram silicon.

The result is much lower latency and because the load on the memory controller is better balanced, getting Gaming performance. The sacrifice that Intel makes is to the efficiency of the Hyper threading.

Every Ram transaction has a time cost. Aggressive sub timings do improve things because it reduces that time cost for each ram transaction. The CPU cannot send a memory request every cycle. CAS14 means 14 cycles to just to set up the memory to be ready for the transfer. Some of the sub timings run in parallel and others are additive to the total time the the settings allow for the transaction to complete. Loose timings extend the time the computer allocates for the transaction to complete. if the actual time the memory needs is less than the allocation, the loose timings are just wasting time.

doubling the frequency of the fabric and increasing the memory controller buffer would make teh chips more Intel like in performance. The 2600x vs 2700x in gaming performance is about the same. Leading me to believe that 6c/12th is probably the optimal level for dual channel memory if you want to do gaming workloads.

25-10-2018, 17:55	#33317
Angelonero87 Senior Member Iscritto dal: Mar 2008 Città: Roma Messaggi: 394	Stavo guardando questo video e ho trovato questo commento interessante su IF https://www.youtube.com/watch?v=PHBsR1Y68G8 brad morris I have worked out the reason why Ryzen has the issues with gaming performance. It is because the data path for the memory traffic from CCX0 and CCX1 to the system memory, over the Infinity fabric, is effectively the same as a three node LAN with a store and forward switch in the middle (AMD call it a CAKE) connecting the three nodes of the network up. Each connection transfers data at 32bytes/cycle at ram speed making the entire trip from cpu to memory relatively slow at about 1600Mhz. The switch has to work like a traffic cop and merge the traffic from both pipes connected to each CCX into a single 32 byte/cycle pipe that connects to the memory controller, cutting the bandwidth available to each CCX in half. The dual channel Ram itself is limited to accepting 32 bytes/cycle so there is no benefit increasing the pipe size connecting the memory to the fabric. Generally the memory access network is fine because memory accesses are by nature bursty and not constant so there are gaps and the queue at the switch in the middle smooths things out. Running cinebench or blender type loads perform well. The available 16 byte/cycle available to each CCX module is enough for the CPU to perform well. If you play a game though, The GPU is connected to the network and needs to access the Memory controller over the same 32 byte/cycle pipe that connects the memory controller to the fabric. Now instead of 16 bytes/cycle available to each CCX, the GPU is also taking say, 30% of the available bandwidth only leaving say 8-12 bytes/cycle available to the threads from eachs CCX. that means the requests have to wait through longe queues at the switch and each thread has to remain idle for a fraction longer waiting for memory access. Faster memory helps because it provides more cycles per second to shift the backlog a the switch. Because the speed from cpu to memory is speed limited, the memory controller doesnt need to buffer much and ends up with either being fully busy or doing nothing Intel uses the ring bus that runs at least twice the frequency of the Ram making the trip from cpu to the memory controller buffer fast with reduced latency. Once in the buffer, the controller to memory link is at the same speed as the AD but it is only a short trip. the controller can write the data to memory as soon as there is a write slot available. Infinity Fabric is a marketing blanket term invented by AMD and actually covers the data transport and the management layer. I am talking about the data transport layer. Make no mistake, it is a network on a Chip. It does not use TCPIP, it has different protocols but the principles of network traffic and network bottlenecks remains the same. Road traffic getting traffic jams at peak hour because two main feeder roads merge into one road with out any extra lanes is exactly the same principle. Increasing ram frequency is the same as giving the merged road a higher speed limit . The infinity Fabric that you are thinking about in terms of frequency is just the transport mechanism. Memory reads and writes are the work that is done by using the transport mechanism and that work takes time to complete. The time the System Ram takes to complete a memory transaction is determined by the CAS timings and sub timings that together determine the total transaction time cost involved. The Fabric has teh capacity to carry 4 memory transactions at a time. A single ram write request takes 60-100 ns to complete depending on how tight the timings are set. The time to complete the transaction and be ready for the next one is what is being reported as Latency in the aida64 latency tests. If the memory is busy with servicing requests from cpu 0-3, the next load of thread memory access requests from cpu4-7 have to wait until the memory is available to get a turn. Threads waiting for access to memory are sitting idle not processing anything. CPU cache is clocked to the CPU clock and is effectively fixed. The Ram frequency sets the speed limit on the data transport. More cycles available on the fabric network, gives the CPU more opportunities for the cpu threads to have their turn to utilize the system Ram. tighter timings means the waiting time before the memory can deal with the next send is lower. AMD and Intel have taken different approaches to accessing memory. The relatively slow Infinity fabric means that the data is speed limited all the way from the CPU to the Memory controller incurring a time cost but the memory controller does not need to buffer anything and processes the requests as they arrive. The time cost is seen as the higher latency scores in the benchmarks. The higher latency does benefit SMT because each thread gets more opportunity to do some work. Intel's ring bus is about double the speed between cpu to memory controller but it relies on the memory controller buffering the fast arriving data an manageing the data access in the last hop to the ram silicon. that makes more efficient use of the available Ram cycles in the last hop from controller to as the Ram silicon. The result is much lower latency and because the load on the memory controller is better balanced, getting Gaming performance. The sacrifice that Intel makes is to the efficiency of the Hyper threading. Every Ram transaction has a time cost. Aggressive sub timings do improve things because it reduces that time cost for each ram transaction. The CPU cannot send a memory request every cycle. CAS14 means 14 cycles to just to set up the memory to be ready for the transfer. Some of the sub timings run in parallel and others are additive to the total time the the settings allow for the transaction to complete. Loose timings extend the time the computer allocates for the transaction to complete. if the actual time the memory needs is less than the allocation, the loose timings are just wasting time. doubling the frequency of the fabric and increasing the memory controller buffer would make teh chips more Intel like in performance. The 2600x vs 2700x in gaming performance is about the same. Leading me to believe that 6c/12th is probably the optimal level for dual channel memory if you want to do gaming workloads.