Quote:
Originariamente inviato da astroimager
Dunque, sto cercando anch'io di capire cosa hanno combinato in questo shrink, e come sono giustificabili i benefici. Non ho però competenza tecnica sufficiente per spiegarti in dettaglio, ma ti riporto un pezzo di Tech Report:
"Most of Shanghai's additional transistors (versus Barcelona) come from its expanded L3 cache, whose performance benefits for many server-class workloads should be fairly obvious. A number of logic changes, many of them cache-related, consume fewer transistors but promise additional benefits. For example, along with the larger cache comes an enhanced data pre-fetch mechanism. This logic attempts to recognize data access patterns and speculatively loads likely-to-be-needed data into cache ahead of time. As caches grow, pre-fetch algorithms often become more aggressive. Shanghai can also probe the L1 and L2 caches in its cores for coherency information twice as often as Barcelona, which gives it double the probe bandwidth. This provision should be particularly helpful when a core has lowered its clock speed to conserve power while idle.
In order to make sure its larger caches don't cause data integrity problems, AMD has built in a new feature it calls L3 Cache Index Disable. This feature allows the CPU to turn off parts of the L3 cache if too many machine-check errors occur. This capability will apparently require OS-level support, and that's not here quite yet. AMD expects "select operating systems" to bring support for this feature next year."
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Per me qualche miglioria in più indubbiamente c'è stata, ma non giustifica la percentuale di IPC di incremento... secondo me hanno fatto tanti bla bla bla per non dire che il B3 aveva dei bug e dei limiti pazzeschi di silicio...a loro conviene osannare di aver fatto un gran lavoro anziché affermare che il B3 era un enorme compromesso tra progetto su carta e limiti di silicio.