Borbone
08-01-2005, 00:54
Questo è il log di Rabit del bios della mia 9800Pro con id XT e chip Samsung 2,8ns:
-- RaBiT v.1.6.1 build 347 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x11C
> PCIR struct offs: 0x17C
> CRC table offs: 0x19D
> CLOCK table offs: 0x87C
Core clock is 378.00 MHz
Memory clock is 338.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1DD
MEM info: MC_CNTL(0x00000022), memory size = 128 Mb
> Memory config: 0x2240
> TV table offs: 0xC702
Active TV type: 'PAL'
> Hardware table: at 0x600, Rev.2
hw_a: 0x330F, hw_b: 0x0000
> DFP table offs: 0x612
DFP table Ver.3, 1 preset(s)
TMDS_PLL(000B01D7), freq = 155.00 MHz
> Connectors Layout table offs: 0x60A
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x92
-- ROM BIOS info --
Desc: R360 Samsung E-DIE DDR BIOS - P/N 113-A07517-100
Info: R350AGP DGD1UN, nhbf2580.848 v611 , 2003/05/06 10:46
Radeon family: Radeon 9800 series
-- Parsing hardware scripts: --
> PLL script at 0x050B
> PLL2 script at 0x05B5
> INIT script at 0x01EF
> MEMORY script at 0x0390
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x01383204) at 0x0535
> SCLK_CNTL(0x00000002) at 0x057B
> MC_TIMING_CNTL(0x1A19A222) at 0x03D4
> MC_CNTL(0x00000022) at 0x0392
> MCLK_CNTL(0xAA3F1212) at 0x0564
> MC_SDRAM_MODE_REG(0x30420042) at 0x03EA
> MC_CHP_IO_OE_CNTL_CD(0x4F304F30) at 0x03CE
> MC_READ_CNTL_CD(0x399B399B) at 0x025F
> MC_READ_CNTL_AB(0x399B399B) at 0x0253
> MC_REFRESH_CNTL(0x00004029) at 0x024D
> MC_CHP_IO_OE_CNTL_AB(0x4F304F30) at 0x03C2
-- In BIOS memory timings --
tWL = 1.0
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 5
tRcdWR = 3
tRP = 5
tRAS = 10
tRRD = 4
tR2W = CL + 3
tWR = 2
tW2R = 2
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 29
tRFC = 17
tRBS = CL + 2.5
tERST = CL - 1.5
tQSREQ = CL - 1.5
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = As specified
tDQS_Adv = As specified
-- Additional hardware info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/2
SDRAM specific: 2**12 rows, 256 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --
Si può affinare da qualche parte? Qualche opzione, timing?
-- RaBiT v.1.6.1 build 347 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x11C
> PCIR struct offs: 0x17C
> CRC table offs: 0x19D
> CLOCK table offs: 0x87C
Core clock is 378.00 MHz
Memory clock is 338.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1DD
MEM info: MC_CNTL(0x00000022), memory size = 128 Mb
> Memory config: 0x2240
> TV table offs: 0xC702
Active TV type: 'PAL'
> Hardware table: at 0x600, Rev.2
hw_a: 0x330F, hw_b: 0x0000
> DFP table offs: 0x612
DFP table Ver.3, 1 preset(s)
TMDS_PLL(000B01D7), freq = 155.00 MHz
> Connectors Layout table offs: 0x60A
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x92
-- ROM BIOS info --
Desc: R360 Samsung E-DIE DDR BIOS - P/N 113-A07517-100
Info: R350AGP DGD1UN, nhbf2580.848 v611 , 2003/05/06 10:46
Radeon family: Radeon 9800 series
-- Parsing hardware scripts: --
> PLL script at 0x050B
> PLL2 script at 0x05B5
> INIT script at 0x01EF
> MEMORY script at 0x0390
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x01383204) at 0x0535
> SCLK_CNTL(0x00000002) at 0x057B
> MC_TIMING_CNTL(0x1A19A222) at 0x03D4
> MC_CNTL(0x00000022) at 0x0392
> MCLK_CNTL(0xAA3F1212) at 0x0564
> MC_SDRAM_MODE_REG(0x30420042) at 0x03EA
> MC_CHP_IO_OE_CNTL_CD(0x4F304F30) at 0x03CE
> MC_READ_CNTL_CD(0x399B399B) at 0x025F
> MC_READ_CNTL_AB(0x399B399B) at 0x0253
> MC_REFRESH_CNTL(0x00004029) at 0x024D
> MC_CHP_IO_OE_CNTL_AB(0x4F304F30) at 0x03C2
-- In BIOS memory timings --
tWL = 1.0
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 5
tRcdWR = 3
tRP = 5
tRAS = 10
tRRD = 4
tR2W = CL + 3
tWR = 2
tW2R = 2
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 29
tRFC = 17
tRBS = CL + 2.5
tERST = CL - 1.5
tQSREQ = CL - 1.5
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = As specified
tDQS_Adv = As specified
-- Additional hardware info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/2
SDRAM specific: 2**12 rows, 256 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --
Si può affinare da qualche parte? Qualche opzione, timing?