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08-05-2017, 09:56 | #41481 | |
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Deve costare 350/360 euro per muovere il mercato.
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08-05-2017, 09:58 | #41482 | |
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08-05-2017, 09:59 | #41483 |
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Assolutamente no ad entrambe le cose che hai detto: non sto trollando, non ha detto tutte cose vere.
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08-05-2017, 10:00 | #41484 | |
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Ma sai, quando le boiate sono troppe, sono troppe.
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08-05-2017, 10:04 | #41485 | |
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E comunque ha detto tutte cose vere: - Hbm2 @512 di banda non ce ne sono e quelle @409 che ci sono.. Sono pure poche. - dai leak, vuoi per qualunque motivo(driver, tecnologie di Vega disabilitate, ecc) ste schede vanno demmerda; - mattoncino di ~500mmq con scarse perf(vedi sopra); Poi non mi ricordo che altro aveva detto, ma sono cose vere se si guardano solo i lati negativi lel
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08-05-2017, 10:13 | #41486 |
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Vabbé ragazzi, stamattina ho piazzato l'ordine per Ryzen + RAM, mi manca solo la mobo.
E Vega, ovviamente... A proposito dei leak, immaginavo che qui si degenerasse e infatti non mi smentite! Comunque il sample a 1200 di clock spero vivamente sia l'anti 1070 perché altrimenti siam messi male. Non possono dire: "Ottimizzata per clock elevati" e poi presentare una roba a 1200 mhz che manco prende la 1080, e non possono nemmeno dire: "Le prestazioni di Vega, confrontate con 1080ti e titan XP, sono buone" se poi piglia mazzate dalla sola 1080. Insomma, stiamo a vedere, comunque confido che quelli siano i leak dell'anti-1070 dai...
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08-05-2017, 10:14 | #41487 |
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Se va meno di una fury....allora
"Aspetta che vi mostro il ca... che me ne frega".... (cit.)
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08-05-2017, 10:18 | #41488 | |
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08-05-2017, 10:23 | #41489 | |
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E tutta una trollata, come pure il fatto che ci sono solo 16000 schede dato che amd aveva detto e non detto che ci sarebbe stata ampia disponibilità...se non avessero fatto il video alla scheda dove si vedevano i connettori ti avrebbero messo una foto ufficiale leakata di vega lunga 35 cm con 4 connettori a 8 pin
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08-05-2017, 10:24 | #41490 |
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Boiate o non boiate bisogna ammettere che questi leak non sono molto entusiasmanti. Ma secondo me non stiamo parlando della top di gamma e inoltre non credo proprio le differenzino solo per il clock, penso ci siano differenze anche a livello di sp. Probabilmente solo la top ne avrà 4096.
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08-05-2017, 10:25 | #41491 | |
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https://www.3dcenter.org/news/was-si...-von-amds-vega per tua comodità di seguito la traduzione (english): What are the known architecture improvements of AMD's Vega? The recent announcement on the confirmed hardware data from AMD's Vega-10 graphics chip has elicited a lot: So in our forum , but also on other websites, which have issued uniform messages - and all wondered why the primary hardware Data between Vega 10 and the former Fiji chip are so uniform. The answer to this question is in what AMD has actually already known for a long time with the " Vega Architecture Previews " from the beginning of the year: The main development of Vega 10 lies in the better graphics chip architecture, where AMD simply wants to make a big leap (which Including significantly higher clock rates) . In keeping with this, our forum is a fine compilation of what has so far been known for architectural changes from Vega and the GCN5 generation. Although GCJ5 ( Vega ) can be a lot more changeable than GCN4 ( Polaris ), even if it is often only the graphic chip experts who can classify the power of the individual features (rough) - Architecture improvements of GCN4 (Polaris) - Instruction buffers have become larger. - Instruction Prefetch is supported. - Primitive Discard Accelerator. - The geometry engines now buffer the meshes themselves, not the Level2 cache. - Improved delta color compression. Architecture improvements from GCN5 (Vega) - Draw Stream Binning Rasterizer ( Source ) . - The rasterizer will now also support Conservative Rasterization. - The instruction buffers are again increased. - The shader units (ALUs) should support a (significantly) higher clock rate. - The shader units will support FP16 calculations with dual performance (to FP32) ( source ) . - The shader units will support Int8 calculations with quad-performance (to FP32). ( Source ) . - The geometry engines will increase the theoretical throughput from a triangle to 2.75 triangles (read, perhaps, only in special cases), which means 11 triangles per clock, rather than 4 as in Fiji ( source ) . - The ROPs are now consumers of the Level2 cache ( source ) , which is why - AMD may also support Rasterizer Ordered Views (this could increase the need for space). - Since the rasterizer now stores tiles in the Level2 cache and also the ROPs are consumers of the Level2 cache, the capacity of the Level2 cache will certainly increase - presumably from 2 MB to 4 MB. - AMD has done more things that have not been mentioned yet. - This also includes a (partial?) Tile-based renderer as with nVidias Maxwell and Pascal chips. In general, the architecture enhancements of GCN5 are considered to be quite potent in our forum - and at least theoretically potent (and how much theory ultimately brings in theory can only be demonstrated by practice) . This is also based on the assumption that AMD at Fiji has apparently left enormous potential: the Fiji computing performance exceeds the previous Hawaii chip by 45% (Radeon R9 Fury X to Radeon R9 390X) , but the achieved 22% performance gain (in the 4K performance index ) is rather meager - and between Fiji and Hawaii there is also an architectural leap from GCN2 to GCN3, which does not really show on its performance results. Should AMD " In this respect, the 15% gain in performance, which was last mentioned at this point, is even considered a "defensive estimate" by the graphics chip architecture (higher clock rates have not yet been included) , some expect more than just this + 15%. Certainly - to achieve nVidias GP102 chip, a higher performance gain purely by the graphics chip architecture would certainly be better, since even taking the clock rate gain of + 40-50% (will not be completely converted 1: 1 in performance, itself If Vega 10 scarcely bandwidth-limited out comes out) would be quite scarce. To get out of Fiji the GP102 chip really to reach, Are 75-80% more per formance necessary - a hard bread with a graphics chip with the same hardware basic data, but also in view of the high clock rate advantage not completely impossible. AMD, however, will have to deliver both points - (for AMD) unusually high clock rates and an architecture advantage of 15% or (better) more. The fact that there is skepticism in this respect and that the user part of the argument on "architectural improvements" do not give anything or understand only minimal performance-effective things is understandable, however, and AMD largely must be attributed to itself. In the past, AMD has advertised more or less every new graphics chip as "extreme" architecture improvements, although the real performance gains on the same clock and the same number of shader units often had to be searched with a magnifying glass. Especially for GCN3 (Tonga & Fiji) as well as GCN4 (Polaris) had been promised in the run-up and due to the full-bodied announcements AMDs some performance gains through the Grafikchip architecture - and was largely disappointed. From this situation, it is quite difficult to come back with the argument of "architecture improvements", because some users (understandably) switch off immediately. According to current knowledge, GCN5 seems to be the (clear) biggest leap within the GCN architecture - a remarkable achievement gain purely through the improved graphics chip architecture is therefore not only expected but also an obligation for AMD. Since some users (understandably) switch off immediately. According to current knowledge, GCN5 seems to be the (clear) biggest leap within the GCN architecture - a remarkable achievement gain purely through the improved graphics chip architecture is therefore not only expected, but also an obligation for AMD. Since some users (understandably) switch off immediately. According to current knowledge, GCN5 seems to be the (clear) biggest leap within the GCN architecture - a remarkable achievement gain purely through the improved graphics chip architecture is therefore not only expected, but also an obligation for AMD.
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08-05-2017, 10:30 | #41492 | |
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08-05-2017, 10:49 | #41493 |
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Grazie... Sono un tonno, bastava controllare gli scores si 3dmark 😂😂😂😂
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08-05-2017, 11:06 | #41494 | |
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08-05-2017, 11:09 | #41495 |
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Che c'entrano gli fp16 coi poligoni per clock?
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08-05-2017, 11:13 | #41496 | |
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08-05-2017, 11:14 | #41497 | |
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08-05-2017, 11:16 | #41498 | |
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Ma poi polaris a chi lo vendono.
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08-05-2017, 11:22 | #41499 |
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maaa secondo voi, se vega andrà bene, le azioni amd torneranno a salire?
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08-05-2017, 11:24 | #41500 |
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Tutti gli orari sono GMT +1. Ora sono le: 12:30.