[capitan_crasy]

X Ren:
Grazie per la segnalazione!

Emergono nuovi dettagli sull'architettura Bulldozer dal programma dell'evento "International Solid-State Circuits Conference 2011" la quale si terrà dal 20 al 24 Febbraio 2011:

4.5 design Solutions for the Bulldozer 32nm Soi 2-core processor 3:15 pM
Module in an 8-core cpu
T. Fischer1, S. Arekapudi2, E. Busta1, C. Dietz3, M. Golden2, S. Hilker2, A. Horiuchi1, K. A. Hurd1,
D. Johnson1, H. McIntyre2, S. Naffziger1, J. Vinh2, J. White4, K. Wilcox4
1AMD, Fort Collins, CO
2AMD, Sunnyvale, CA
3AMD, Austin, TX
4AMD, Boxborough, MA
The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metalgate
SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves
performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the
same process. The design reduces the number of gates/cycle relative to prior designs, achieving
3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2.

4.6 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core
M. Golden, S. Arekapudi, J. Vinh, AMD
A 40-instruction out-of-order scheduler issues four operations per cycle and supports single-cycle operation wakeup. The integer execution unit supports single-cycle bypass between four functional units. Critical paths are implemented without exotic circuit techniques or heavy reliance on full-custom design. Architectural choices minimize power consumption.

14.3 An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing
D. Weiss, M. Dreesen, M. Ciraula, C. Henrion, C. Helt, R. Freese, T. Miles, A. Karegar, R. Schreiber, B. Schneller, J. Wuu, AMD
An 8MB level 3 cache, composed of 4 independent 2MB subcaches, is built on a 32nm SOI process. It features column-select aliasing to improve area efficiency, supply gating and floating bitlines to reduce leakage power, and centralized redundant row and column blocks to improve yield and testability. The cache operates above 2.4GHz at 1.1V.

Un modulo Bulldozer con due core sarà composto da 213 milioni di transistors costruiti a 32nm, la tensione di funzionamento sarà da un minimo di 0.8V ad un massimo di 1.30V.
Le frequenze di clock previste sono di 3.50Ghz+ compresa la cache L2, per un totale di 30.9mm2.
La cache L3 sarà di 8MB divise in 4 subcaches indipendenti; la frequenza sarà di 2.40Ghz ad una tensione di 1.1V.
E probabile che AMD rilascerà altre informazioni proprio durante questo evento.


Intero programma ISSCC 2011 in formato PDF